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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt86vl34 quad t1/e1/j1 framer/liu combo - e1 register description january 2007 rev. v1.2.0 general description the xrt86vl34 is a four-channel 1.544 mbit/s or 2.048 mbit/s ds1/e1/j1 framer and liu integrated solution featuring r 3 technology (relayless, reconfigurable, redundancy). the physical interface is optimized with internal impedance, and with the patented pad structure, the xrt86vl34 provides protection from power failures and hot swapping. the xrt86vl34 contains an integrated ds1/e1/j1 framer and liu which provide ds1/e1/j1 framing and error accumulation in accordance with ansi/itu_t specifications. each framer has its own framing synchronizer and transmit-receive slip buffers. the slip buffers can be independently enabled or disabled as required and can be configured to frame to the common ds1/e1/j1 signal formats. each framer block contains its own transmit and receive t1/e1/j1 framing function. there are 3 transmit hdlc controllers per channel which encapsulate contents of the transmit hdlc buffers into lapd message frames. there are 3 receive hdlc controllers per channel which extract the payload content of receive lapd message frames from the incoming t1/e1/j1 data stream and write the contents into the receive hdlc buffers. each framer also contains a transmit and overhead data input port, which permits data link terminal equipment direct access to the outbound t1/e1/j1 frames. likewise, a receive overhead output data port permits data link terminal equipment direct access to the data link bits of the inbound t1/e1/j1 frames. the xrt86vl34 fully meets all of the latest t1/e1/j1 specifications: ansi t1/e1.107-1988, ansi t1/ e1.403-1995, ansi t1/e1.231-1993, ansi t1/ e1.408-1990, at&t tr 62411 (12-90) tr54016, and itu g-703, g.704, g706 and g.733, at&t pub. 43801, and ets 300 011, 300 233, jt g.703, jt g.704, jt g706, i.431. extensive test and diagnostic functions include loop-backs, boundary scan, pseudo random bit sequence (prbs) test pattern generation, performance monitor, bit error rate (ber) meter, forced error insertion, and lapd unchannelized data payload processing according to itu-t standard q.921. applications and features (next page) f igure 1. xrt86vl34 4- channel ds1 (t1/e1/j1) f ramer /liu c ombo performance monitor prbs generator & analyser hdlc/lapd controllers liu & loopback control dma interface signaling & alarms jtag wr ale_as rd rdy_dtack p select a[13:0] d[7:0] microprocessor interface 4 3 tx serial clock rx serial clock 8khz sync osc back plane 1.544-16.384 mbit/s local pcm highway st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out rtip rring ttip tring external data link controller tx overhead in rx overhead out xrt86vl34 1 of 4-channels tx framer llb lb system (terminal) side line side 1:1 turns ratio 1:2 turns ratio memory intel/motorola p configuration, control & status monitor rxlos txon int
xrt86vl34 2 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 applications ? high-density t1/e1/j1 interfaces for multiplexers, switches, lan routers and digital modems ? sonet/sdh terminal or add/drop multiplexers (adms) ? t1/e1/j1 add/drop multiplexers (mux) ? channel service units (csus): t1/e1/j1 and fractional t1/e1/j1 ? digital access cross-connect system (dacs) ? digital cross-connect systems (dcs) ? frame relay switches and access devices (frads) ? isdn primary rate interfaces (pra) ? pbxs and pcm channel bank ? t3 channelized access concentrators and m13 mux ? wireless base stations ? atm equipment with integrated ds1 interfaces ? multichannel ds1 test equipment ? t1/e1/j1 performance monitoring ? voice over packet gateways ? routers features ? four independent, full duplex ds1 tx and rx framer/lius ? two 512-bit (two-frame) elastic store, pcm frame slip buffers (fifo) on tx and rx provide up to 8.192 mhz asynchronous back plane connections with jitter and wander attenuation ? supports input pcm and signaling data at 1.544, 2.048, 4.096 and 8.192 mbits. also supports 4-channel multiplexed 12.352/16.384 (hmvip/h.100) mbit/s on the back plane bus ? programmable output clocks for fractional t1/e1/j1 ? supports channel associated signaling (cas) ? supports common ch annel signalling (ccs) ? supports isdn primary rate interface (isdn pri) signaling ? extracts and inserts robbed bit signaling (rbs) ? 3 integrated hdlc controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) ? hdlc controllers support ss7 ? timeslot assignable hdlc ? v5.1 or v5.2 interface ? automatic performance report generation (pmon status) can be inserted into the transmit lapd interface every 1 second or for a single transmission ? alarm indication signal with customer installation signature (ais-ci) ? remote alarm indication with customer installation (rai-ci) ? gapped clock interface mode for transmit and receive.
xrt86vl34 3 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description ? intel/motorola and power pc interfaces for configuration, control and status monitoring ? parallel search algorithm for fast frame synchronization ? wide choice of t1 framing structures: sf/d4, esf, slc ? 96, t1dm and n-frame (non-signaling) ? direct access to d and e channels for fast transmission of data link information ? prbs, qrss, and network loop code generation and detection ? programmable interrupt output pin ? supports programmed i/o and dma modes of read-write access ? each framer block encodes and decodes the t1/e1/j1 frame serial data ? detects and forces red (sai), yellow (rai) and blue (ais) alarms ? detects oof, lof, los errors and cofa conditions ? loopbacks: local (llb) and line remote (lb) ? facilitates inverse multiplexing for atm ? performance monitor with one second polling ? boundary scan (ieee 1149.1) jtag test port ? accepts external 8khz sync reference ? 1.8v inner core ? 3.3v cmos operation with 5v tolerant inputs ? 225-pin pbga package with -40 c to +85 c operation ordering information p art n umber p ackage o perating t emperature r ange xrt86vl34ib 225 plastic ball grid array -40 c to +85 c
xrt86vl34 i quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 list of paragraphs 1.0 register descriptions - e1 mode ........................................................................................... .....9 2.0 line interface unit (liu section) registers .......................................................................144
xrt86vl34 a rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description list of figures figure 1.: xrt86vl34 4-channel ds1 (t1/e1/j1) framer/liu combo ................................................................ ............. 1
xrt86vl34 i quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 list of tables t able 1: r egister s ummary ............................................................................................................................... .......................... 4 t able 1: c lock s elect r egister (csr) h ex a ddress : 0 xn 100 .......................... 9 t able 2: l ine i nterface c ontrol r egister (licr) h ex a ddress : 0 xn 101........................ 11 t able 3: f raming s elect r egister (fsr) h ex a ddress : 0 xn 107 ....................... 13 t able 4: a larm g eneration r egister (agr) h ex a ddress : 0 xn 108 ......................... 17 t able 5: s ynchronization mux r egister (smr) h ex a ddress : 0 xn 109........................ 19 t able 6: t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 xn 10a ........................ 22 t able 7: f raming c ontrol r egister (fcr) h ex a ddress : 0 xn 10b....................... 25 t able 8: r eceive s ignaling & d ata l ink s elect r egister (rsdlsr) h ex a ddress : 0 xn 10c ....................... 27 t able 9: r eceive s ignaling c hange r egister 0 (rscr 0) h ex a ddress : 0 xn 10d ..................... 29 t able 10: r eceive s ignaling c hange r egister 1 (rscr 1) h ex a ddress : 0 xn 10e .................. 29 t able 11: r eceive s ignaling c hange r egister 2 (rscr 2) h ex a ddress : 0 xn 10f .................. 29 t able 12: r eceive s ignaling c hange r egister 3 (rscr 3) h ex a ddress : 0 xn 110.................. 30 t able 13: r eceive n ational b its r egister (rnbr) h ex a ddress : 0 xn 111...................... 31 t able 14: r eceive e xtra b its r egister (rebr) h ex a ddress : 0 xn 112..................... 32 t able 15: d ata l ink c ontrol r egister (dlcr1) h ex a ddress : 0 xn 113 ....................... 34 t able 16: t ransmit d ata l ink b yte c ount r egister (tdlbcr1) h ex a ddress : 0 xn 114..................... 36 t able 17: r eceive d ata l ink b yte c ount r egister (rdlbcr1) h ex a ddress : 0 xn 115 ...................... 37 t able 18: s lip b uffer c ontrol r egister (sbcr) h ex a ddress : 0 xn 116...................... 38 t able 19: fifo l atency r egister (ffolr) h ex a ddress : 0 xn 117 ....................... 39 t able 20: dma 0 (w rite ) c onfiguration r egister (d0wcr) h ex a ddress : 0 xn 118...................... 40 t able 21: dma 1 (r ead ) c onfiguration r egister (d1rcr) h ex a ddress : 0 xn 119 ...................... 41 t able 22: i nterrupt c ontrol r egister (icr) h ex a ddress : 0 xn 11a ..................... 42 t able 23: lapd s elect r egister (lapdsr) h ex a ddress : 0 xn 11b ....................... 43 t able 24: p erformance r eport c ontrol r egister (prcr) h ex a ddress : 0 xn 11d ..................... 43 t able 25: g apped c lock c ontrol r egister (gccr) h ex a ddress : 0 xn 11e ...................... 44 t able 26: t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 xn 120 ..................... 45 t able 27: t ransmit i nterface s peed w hen m ultiplexed m ode is d isabled (t x muxen = 0) ................................................ 47 t able 28: t ransmit i nterface s peed when m ultiplexed m ode is e nabled (t x muxen = 1).................................................. 48 t able 29: prbs c ontrol a nd s tatus r egister 0 (prbscsr0) h ex a ddress : 0 xn 121..................... 49 t able 30: r eceive i nterface c ontrol r egister (ricr) h ex a ddress : 0 xn 122...................... 51 t able 31: r eceive i nterface s peed w hen m ultiplexed m ode is d isabled (t x muxen = 0) .................................................. 53 t able 32: r eceive i nterface s peed when m ultiplexed m ode is e nabled (t x muxen = 1).................................................... 54 t able 33: prbs c ontrol and s tatus r egister 1 (prbscsr1) h ex a ddress : 0 xn 123 ..................... 55 t able 34: l oopback c ode c ontrol r egister (lccr) h ex a ddress : 0 xn 124 ....................... 57 t able 35: t ransmit l oopback c oder r egister (tlcr) h ex a ddress : 0 xn 125 ....................... 57 t able 36: r eceive l oopback a ctivation c ode r egister (rlacr) h ex a ddress : 0 xn 126..................... 57 t able 37: r eceive l oopback d eactivation c ode r egister (rldcr) h ex a ddress : 0 xn 127 ......................... 57 t able 38: d efect d etection e nable r egister (dder) h ex a ddress : 0 xn 129........................ 57 t able 39: t ransmit s a s elect r egister (tsasr) h ex a ddress : 0 xn 130....................... 58 t able 40: t ransmit s a a uto c ontrol r egister 1 (tsacr1) h ex a ddress : 0 xn 131 ....................... 60 t able 41: c onditions on r eceive side w hen tsacr1 bits a re enabled ................................................................................ 61 t able 42: t ransmit s a a uto c ontrol r egister 2 (tsacr2) h ex a ddress : 0 xn 132 .......................... 62 t able 43: c onditions on r eceive side w hen tsacr2 bits enabled ....................................................................................... 63 t able 44: t ransmit s a 4 r egister (tsa4r) h ex a ddress : 0 xn 133 ..................... 64 t able 45: t ransmit s a 5 r egister (tsa5r) h ex a ddress : 0 xn 134 ..................... 64 t able 46: t ransmit s a 6 r egister (tsa6r) h ex a ddress : 0 xn 135 ..................... 64 t able 47: t ransmit s a 7 r egister (tsa7r) h ex a ddress : 0 xn 136 ..................... 64 t able 48: t ransmit s a 8 r egister (tsa8r) h ex a ddress : 0 xn 137 ..................... 65 t able 49: r eceive s a 4 r egister (rsa4r) h ex a ddress : 0 xn 13b ...................... 66 t able 50: r eceive s a 5 r egister (rsa5r) h ex a ddress : 0 xn 13c...................... 66 t able 51: r eceive s a 6 r egister (rsa6r) h ex a ddress : 0 xn 13d...................... 66 t able 52: r eceive s a 7 r egister (rsa7r) h ex a ddress : 0 xn 13e ...................... 67 t able 53: r eceive s a 8 r egister (rsa8r) h ex a ddress : 0 xn 13f ...................... 67 t able 54: d ata l ink c ontrol r egister (dlcr2) h ex a ddress : 0 xn 143 ................... 68 t able 55: t ransmit d ata l ink b yte c ount r egister (tdlbcr2) h ex a ddress : 0 xn 144..................... 70 t able 56: r eceive d ata l ink b yte c ount r egister (rdlbcr2) h ex a ddress : 0 xn 145 ...................... 71 t able 57: d ata l ink c ontrol r egister (dlcr3) h ex a ddress : 0 xn 153 ..................... 72 t able 58: t ransmit d ata l ink b yte c ount r egister (tdlbcr3) h ex a ddress : 0 xn 154....................... 74 t able 59: r eceive d ata l ink b yte c ount r egister (rdlbcr3) h ex a ddress : 0 xn 155 ..................... 75 t able 60: d evice id r egister (devid) h ex a ddress : 0 xn 1fe ...................... 76 t able 61: r evision id r egister (revid) h ex a ddress : 0 xn 1ff................... 76 t able 62: t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0x n 300 to 0 xn 31f...................... 77 t able 63: t ransmit u ser c ode r egister 0 - 31 (tucr 0-31) h ex a ddress : 0 xn 320 to 0 xn 33f.................... 79
xrt86vl34 ii rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 64: t ransmit s ignaling c ontrol r egister 0-31 (tscr 0-31) h ex a ddress : 0 xn 340 to 0 xn 35f ..................... 80 t able 65: r eceive c hannel c ontrol r egister x (rccr 0-31) h ex a ddress : 0 xn 360 to 0 xn 37f ..................... 83 t able 66: r eceive u ser c ode r egister 0-31 (rucr 0-31) h ex a ddress : 0 xn 380 to 0 xn 39f ..................... 85 t able 67: r eceive s ignaling c ontrol r egister 0-31 (rscr 0-31) h ex a ddress : 0 xn 3a0 to 0 xn 3bf ...................... 86 t able 68: r eceive s ubstitution s ignaling r egister 0-31 (rssr 0-31) h ex a ddress 0 xn 3c0 to 0 xn 3df ...................... 88 t able 69: r eceive s ignaling a rray r egister 0 - 31 (rsar 0-31) h ex a ddress : 0x n 500 to 0 xn 51f ...................... 89 t able 70: lapd b uffer 0 c ontrol r egister (lapdbcr0) h ex a ddress : 0 xn 600 ........................................ 90 t able 71: lapd b uffer 1 c ontrol r egister (lapdbcr1) h ex a ddress : 0 xn 700 ........................................ 90 t able 72: pmon r eceive l ine c ode v iolation c ounter msb (rlcvcu) h ex a ddress : 0 xn 900 ....................... 91 t able 73: pmon r eceive l ine c ode v iolation c ounter lsb (rlcvcl) h ex a ddress : 0 xn 901 ....................... 91 t able 74: pmon r eceive f raming a lignment b it e rror c ounter msb (rfaecu) h ex a ddress : 0 xn 902 ....................... 92 t able 75: pmon r eceive f raming a lignment b it e rror c ounter lsb (rfaecl) h ex a ddress : 0 xn 903........................ 92 t able 76: pmon r eceive s everely e rrored f rame c ounter (rsefc) h ex a ddress : 0 xn 904 ........................ 93 t able 77: pmon r eceive crc-4 b it e rror c ounter - msb (rsbbecu) h ex a ddress : 0 xn 905 ........................ 93 t able 78: pmon r eceive crc-4 b lock e rror c ounter - lsb (rsbbecl) h ex a ddress : 0 xn 906 ........................ 93 t able 79: pmon r eceive f ar -e nd bl ock e rror c ounter - msb (rfebecu) h ex a ddress : 0 xn 907....................... 94 t able 80: pmon r eceive f ar e nd b lock e rror c ounter -lsb (rfebecl) h ex a ddress : 0 xn 908 ........................ 94 t able 81: pmon r eceive s lip c ounter (rsc) h ex a ddress : 0 xn 909 ..................... 95 t able 82: pmon r eceive l oss of f rame c ounter (rlfc) h ex a ddress : 0 xn 90a ...................... 95 t able 83: pmon r eceive c hange of f rame a lignment c ounter (rcfac) h ex a ddress : 0 xn 90b ....................... 95 t able 84: pmon lapd f rame c heck s equence e rror c ounter 1 (lfcsec1) h ex a ddress : 0 xn 90c....................... 96 t able 85: pmon prbs b it e rror c ounter msb (pbecu) h ex a ddress : 0 xn 90d ................... 96 t able 86: pmon prbs b it e rror c ounter lsb (pbecl) h ex a ddress : 0 xn 90e................... 96 t able 87: pmon t ransmit s lip c ounter (tsc) h ex a ddress : 0 xn 90f .................... 97 t able 88: pmon e xcessive z ero v iolation c ounter msb (ezvcu) h ex a ddress : 0 xn 910 ....................... 97 t able 89: pmon e xcessive z ero v iolation c ounter lsb (ezvcl) h ex a ddress : 0 xn 911 ....................... 97 t able 90: pmon f rame c heck s equence e rror c ounter 2 (lfcsec2) h ex a ddress : 0 xn 91c ....................... 98 t able 91: pmon f rame c heck s equence e rror c ounter 3 (lfcsec3) h ex a ddress : 0 xn 92c ....................... 98 t able 92: b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 xn b00 ........................ 99 t able 93: b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 xn b01 ...................... 101 t able 94: a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 xn b02 ...................... 103 t able 95: a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 xn b03 ...................... 106 t able 96: f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 xn b04 ................... 108 t able 97: f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 xn b05 .................... 111 t able 98: d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 xn b06 ..................... 113 t able 99: d ata l ink i nterrupt e nable r egister 1 (dlier1) h ex a ddress : 0 xn b07 ....................... 115 t able 100: s lip b uffer i nterrupt s tatus r egister (sbisr) h ex a ddress : 0 xn b08 ................. 117 t able 101: s lip b uffer i nterrupt e nable r egister (sbier) h ex a ddress : 0 xn b09 ..................... 120 t able 102: r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) h ex a ddress : 0 xn b0a ...................... 122 t able 103: r eceive l oopback c ode i nterrupt e nable r egister (rlcier) h ex a ddress : 0 xn b0b .................... 124 t able 104: r eceive sa i nterrupt s tatus r egister (rsaisr) h ex a ddress : 0 xn b0c .................. 125 t able 105: r eceive sa i nterrupt e nable r egister (rsaier) h ex a ddress : 0 xn b0d ................... 128 t able 106: e xcessive z ero s tatus r egister (exzsr) h ex a ddress : 0 xn b0e................. 131 t able 107: e xcessive z ero e nable r egister (exzer) h ex a ddress : 0 xn b0f ................... 132 t able 108: r x los/crc i nterrupt s tatus r egister (rlcisr) h ex a ddress : 0 xn b12 ................. 133 t able 109: r x los/crc i nterrupt e nable r egister (rlcier) h ex a ddress : 0 xn b13 .................. 135 t able 110: d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 xn b16 ..................... 136 t able 111: d ata l ink i nterrupt e nable r egister 2 (dlier2) h ex a ddress : 0 xn b17 .................... 138 t able 112: d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 xn b26 ..................... 140 t able 113: d ata l ink i nterrupt e nable r egister 3 (dlier3) h ex a ddress : 0 xn b27 ................... 142 t able 114: liu c hannel c ontrol r egister 0 (liuccr0) h ex a ddress : 0 x 0f n 0.................. 144 t able 115: e qualizer c ontrol and t ransmit l ine b uild o ut ............................................................................................... 146 t able 116: liu c hannel c ontrol r egister 1 (liuccr1) h ex a ddress : 0 x 0f n 1.................. 147 t able 117: liu c hannel c ontrol r egister 2 (liuccr2) h ex a ddress : 0 x 0f n 2.................. 149 t able 118: liu c hannel c ontrol r egister 3 (liuccr3) h ex a ddress : 0 x 0f n 3.................. 151 t able 119: liu c hannel c ontrol i nterrupt e nable r egister (liuccier) h ex a ddress : 0 x 0f n 4 ................... 153 t able 120: liu c hannel c ontrol s tatus r egister (liuccsr) h ex a ddress : 0 x 0f n 5 .................... 155 t able 121: liu c hannel c ontrol i nterrupt s tatus r egister (liuccisr) h ex a ddress : 0 x 0f n 6 .................... 158 t able 122: liu c hannel c ontrol c able l oss r egister (liuccccr) h ex a ddress : 0 x 0f n 7 .................... 160 t able 123: liu c hannel c ontrol a rbitrary r egister 1 (liuccar1) h ex a ddress : 0 x 0f n 8 .................... 160 t able 124: liu c hannel c ontrol a rbitrary r egister 2 (liuccar2) h ex a ddress : 0 x 0f n 9 .................... 160 t able 125: liu c hannel c ontrol a rbitrary r egister 3 (liuccar3) h ex a ddress : 0 x 0f n a .................... 161 t able 126: liu c hannel c ontrol a rbitrary r egister 4 (liuccar4) h ex a ddress : 0 x 0f n b .................... 161 t able 127: liu c hannel c ontrol a rbitrary r egister 5 (liuccar5) h ex a ddress : 0 x 0f n c .................... 161 t able 128: liu c hannel c ontrol a rbitrary r egister 6 (liuccar6) h ex a ddress : 0 x 0f n d .................... 162 t able 129: liu c hannel c ontrol a rbitrary r egister 7 (liuccar7) h ex a ddress : 0 x 0f n e .................... 162
xrt86vl34 iii quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 130: liu c hannel c ontrol a rbitrary r egister 8 (liuccar8) h ex a ddress : 0 x 0f n f .................... 162 t able 131: liu g lobal c ontrol r egister 0 (liugcr0) h ex a ddress : 0 x 0fe0 .................. 163 t able 132: liu g lobal c ontrol r egister 1 (liugcr1) h ex a ddress : 0 x 0fe1 .................. 164 t able 133: liu g lobal c ontrol r egister 2 (liugcr2) h ex a ddress : 0 x 0fe2 .................. 166 t able 134: liu g lobal c ontrol r egister 3 (liugcr3) h ex a ddress : 0 x 0fe4 .................. 166 t able 135: liu g lobal c ontrol r egister 4 (liugcr4) h ex a ddress : 0 x 0fe9 .................. 167 t able 136: liu g lobal c ontrol r egister 5 (liugcr5) h ex a ddress : 0 x 0fea .................. 168
xrt86vl34 4 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description description of the control registers - e1 mode all address on this register description is shown in hex format, where n indicates channels 0-3 in the 4-channel device. t able 1: r egister s ummary f unction s ymbol h ex control registers (0xn100 - 0xn1ff) clock and select register csr 0xn100 line interface control register licr 0xn101 reserved - 0xn102 - 0xn106 framing select register fsr 0xn107 alarm generation register agr 0xn108 synchronization mux register smr 0xn109 transmit signaling and data link select register tsdlsr 0xn10a framing control register fcr 0xn10b receive signaling & data link select register rsdlsr 0xn10c receive signaling change register 0 rscr0 0xn10d receive signaling change register 1 rscr1 0xn10e receive signaling change register 2 rscr2 0xn10f receive signaling change register 3 rscr3 0xn110 receive national bits register rnbr 0xn111 receive extra bits register rebr 0xn112 data link control register 1 dlcr1 0xn113 transmit data link byte count register 1 tdlbcr1 0xn114 receive data link byte count register 1 rdlbcr1 0xn115 slip buffer control register sbcr 0xn116 fifo latency register fifolr 0xn117 dma 0 (write) configuration register d0wcr 0xn118 dma 1 (read) configuration register d1rcr 0xn119 interrupt control register icr 0xn11a lapd select register lapdsr 0xn11b reserved - t1 mode only - 0xn11c performance report control register prcr 0xn11d gapped clock control register gccr 0xn11e transmit interface control register ticr 0xn120 prbs control & status register 0 prbscsr0 0xn121
xrt86vl34 5 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 receive interface control register ricr 0xn122 prbs control & status register 1 prbscsr1 0xn123 for t1 mode only - 0xn124 - 0xn127 defect detection enable register dder 0xn129 transmit sa select register tsasr 0xn130 transmit sa auto control register 1 tsacr1 0xn131 transmit sa auto control register 2 tsacr2 0xn132 transmit sa4 register tsa4r 0xn133 transmit sa5 register tsa5r 0xn134 transmit sa6 register tsa6r 0xn135 transmit sa7 register tsa7r 0xn136 transmit sa8 register tsa8r 0xn137 receive sa4 register rsa4r 0xn13b receive sa5 register rsa5r 0xn13c receive sa6 register rsa6r 0xn13d receive sa7 register rsa7r 0xn13e receive sa8 register rsa8r 0xn13f reserved - t1 mode only - 0xn142 data link control register 2 dlcr2 0xn143 transmit data link byte count register 2 tdlbcr2 0xn144 receive data link byte count register 2 rdlbcr2 0xn145 data link control register 3 dlcr3 0xn153 transmit data link byte count register 3 tdlbcr3 0xn154 receive data link byte count register 3 rdlbcr3 0xn155 device id register devid 0xn1fe revision number register revid 0xn1ff time slot (payload) control (0xn300 - 0xn3ff) transmit channel control register 0-31 tccr 0-31 0xn300 - 0xn31f user code register 0-31 tucr 0-31 0xn320 - 0xn33f transmit signaling control register 0 -31 tscr 0-31 0xn340 - 0xn35f t able 1: r egister s ummary f unction s ymbol h ex
xrt86vl34 6 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description receive channel control register 0-31 rccr 0-31 0xn360 - 0xn37f receive user code register 0-31 rucr 0-31 0xn380 - 0xn39f receive signaling control register 0-31 rscr 0-31 0xn3a0 - 0xn3bf receive substitution signaling register 0-31 rssr 0-31 0xn3c0 - 0xn3df receive signaling array (0xn500 - 0xn51f) receive signaling array register 0 rsar0-31 0xn500 - 0xn51f lapdn buffer 0 lapd buffer 0 control register lapdbcr0 0xn600 - 0xn660 lapdn buffer 1 lapd buffer 1 control register lapdbcr1 0xn700 - 0xn760 performance monitor receive line code violation counter: msb rlcvcu 0xn900 receive line code violation counter: lsb rlcvcl 0xn901 receive frame alignment error counter: msb rfaecu 0xn902 receive frame alignment error counter: lsb rfaecl 0xn903 receive severely errored frame counter rsefc 0xn904 receive synchronization bit (crc-6 (t1) crc-4 (e1) block) error counter: msb rsbbecu 0xn905 receive synchronization bit (crc-6 (t1) crc-4 (e1) block) error counter: lsb rsbbecl 0xn906 receive far-end block error counter: msb rfebecu 0xn907 receive far-end block error counter: lsb rfebecl 0xn908 receive slip counter rsc 0xn909 receive loss of frame counter rlfc 0xn90a receive change of frame alignment counter rcfac 0xn90b lapd frame check sequence error counter 1 lfcsec1 0xn90c prbs bit error counter: msb pbecu 0xn90d prbs bit error counter: lsb pbecl 0xn90e transmit slip counter tsc 0xn90f t able 1: r egister s ummary f unction s ymbol h ex
xrt86vl34 7 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 excessive zero violation counter: msb ezvcu 0xn910 excessive zero violation counter: lsb ezvcl 0xn911 lapd frame check sequence error counter 2 lfcsec2 0xn91c lapd frame check sequence error counter 3 lfcsec3 0xn92c interrupt generation/enable register address map (0xnb00 - 0xnb41) block interrupt status register bisr 0xnb00 block interrupt enable register bier 0xnb01 alarm & error interrupt status register aeisr 0xnb02 alarm & error interrupt enable register aeier 0xnb03 framer interrupt status register fisr 0xnb04 framer interrupt enable register fier 0xnb05 data link status register 1 dlsr1 0xnb06 data link interrupt enable register 1 dlier1 0xnb07 slip buffer interrupt status register sbisr 0xnb08 slip buffer interrupt enable register sbier 0xnb09 receive loopback code interrupt and status register rlcisr 0xnb0a receive loopback code interrupt enable register rlcier 0xnb0b receive sa (sa6) interrupt status register rsaisr 0xnb0c receive sa (sa6) interrupt enable register rsaier 0xnb0d excessive zero status register exzsr 0xnb0e excessive zero enable register exzer 0xnb0f reserved - t1 mode only - 0xnb10 - 0xnb11 rxlos/crc interrupt status register rlcisr 0xnb12 rxlos/crc interrupt enable register rlcier 0xnb13 data link status register 2 dlsr2 0xnb16 data link interrupt enable register 2 dlier2 0xnb17 reserved - t1 mode only - 0xnb18 - 0xnb19 data link status register 3 dlsr3 0xnb26 data link interrupt enable register 3 dlier3 0xnb27 reserved - t1 mode only - 0xnb28 - 0xnb29 reserved - t1 mode only ciaier 0xnb40 - 0xnb41 liu register summary - channel control registers liu channel control register 0 liuccr0 0x0fn0 t able 1: r egister s ummary f unction s ymbol h ex
xrt86vl34 8 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description liu channel control register 1 liuccr1 0x0fn1 liu channel control register 2 liuccr2 0x0fn2 liu channel control register 3 liuccr3 0x0fn3 liu channel control interrupt enable register liuccier 0x0fn4 liu channel control status register liuccsr 0x0fn5 liu channel control interrupt status register liuccisr 0x0fn6 liu channel control cable loss register liuccccr 0x0fn7 liu channel control arbitrary register 1 liuccar1 0x0fn8 liu channel control arbitrary register 2 liuccar2 0x0fn9 liu channel control arbitrary register 3 liuccar3 0x0fna liu channel control arbitrary register 4 liuccar4 0x0fnb liu channel control arbitrary register 5 liuccar5 0x0fnc liu channel control arbitrary register 6 liuccar6 0x0fnd liu channel control arbitrary register 7 liuccar7 0x0fne liu channel control arbitrary register 8 liuccar8 0x0fnf reserved - 0x0f80 - 0x0fdf liu register summary - global control registers liu global control register 0 liugcr0 0x0fe0 liu global control register 1 liugcr1 0x0fe1 liu global control register 2 liugcr2 0x0fe2 liu global control register 3 liugcr3 0x0fe4 liu global control register 4 liugcr4 0x0fe9 liu global control register 5 liugcr5 0x0fea reserved - 0x0feb - 0x0fff t able 1: r egister s ummary f unction s ymbol h ex
xrt86vl34 9 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1.0 register descriptions - e1 mode all address on this register description is shown in hex format, where n indicates channels 0-3 in the 4-channel device. t able 1: c lock s elect r egister (csr) h ex a ddress : 0 x n100 b it f unction t ype d efault d escription -o peration 7 lcv insert r/w 0 line code violation insertion this bit is used to force a line code violation (lcv) on the transmit output of ttip/tring. a ?0? to ?1? transition on this bit will cause a single lcv to be inserted on the transmit output of ttip/tring. 6 set t1 mode r/w 0 t1/e1 mode select this bit is used to program the individual channel to operate in either t1 or e1 mode. 0 = configures the selected channel to operate in e1 mode. 1 = configures the selected channel to operate in t1 mode. 5 sync all transmit - ters to 8khz r/w 0 sync all transmit framers to 8khz this bit permits the user to configure each of the four (4) transmit e1 framer blocks to synchronize their ?transmit output? frame alignment with the 8khz signal that is derived from the mclk pll, as described below. 0 - disables the ?sync all transmit framers to 8khz? feature for all 4 channels. 1 - enables the ?sync all transmit framers to 8khz? feature for all 4 channels. n ote : writing to this bit in register 0x0100 will enable this feature for all 4 channels. n ote : this bit is only active if the mclk pll is used as the ?timing source? for the transmit e1 framer? blocks. css[1:0] of this register allows users to select the transmit source of the framer. 4 clock loss detect r/w 1 clock loss detect enable/disable select this bit enables a clock loss protection feature for the framer when - ever the recovered line clock is used as the timing source for the trans - mit section. if the liu loses clock recovery, the clock distribution block will detect this occurrence and automatically begin to use the internal clock derived from mclk pll as the transmit source, until the liu is able to regain clock recovery. 0 = disables the clock loss protection feature. 1 = enables the clock loss protection feature. n ote : this bit needs to be enabled in order to detect the clock loss detection interrupt status (address: 0xnb00, bit 5) 3:2 reserved r/w 00 reserved
xrt86vl34 10 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1:0 css[1:0] r/w 01 clock source select these bits select the timing source for the transmit e1 framer block. these bits can also determine the direction of txserclk, txsync, and txmsync in base rate operation mode (2.048mhz clock mode). in base rate (2.048mhz clock mode): t able 1: c lock s elect r egister (csr) h ex a ddress : 0 x n100 b it f unction t ype d efault d escription -o peration n ote : txsync/txmsync can be programmed as input or outpu t depending on the setting of sync inv bit in register address 0xn109, bit 4. please see register description for the synchronization mux register (smr - 0xn109). n otes : in high-speed or multiplexed modes, txserclk, txsync, a nd txmsync are all configured as inputs only. css[1:0] t ransmit s ource for the t ransmit e1 f ramer b lock d irection of t x serclk 00/11 loop timing mode the recovered line clock is cho- sen as the timing source. output 01 external timing mode the transmit serial input clock from the txserclk_n input pin is chosen as the timing source. input 10 internal timing mode the mclk pll is chosen as the timing source. output
xrt86vl34 11 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 2: l ine i nterface c ontrol r egister (licr) h ex a ddress : 0 x n101 b it f unction t ype d efault d escription -o peration 7 force_los r/w 0 force transmit los (to the line side) this bit permits the user to configure the transmit direction circuitry (within the channel) to transmit the los pattern to the remote terminal equipment, as described below. 0 - configures the transmit direction circuitry to transmit ?normal? traffic. 1 - configures the transmit direction circuitry to transmit the los pattern. 6 sr r/w 0 single rail mode this bit can only be set if the liu block is also set to single rail mode. see register 0x0fe0, bit 7. 0 - dual rail 1 - single rail 5:4 lb[1:0] r/w 00 framer loopback selection these bits are used to select any of the following loop-back modes for the framer section. for liu loopback modes, see the liu configuration registers. 3:2 reserved r/w 0 reserved lb[1:0] t ypes o f l oop b ack s elected 00 normal mode (no loopback) 01 framer local loopback: when framer local loopback is enabled, the transmit pcm input data is looped back to the receive pcm out- put data. the receive input data at rtip/rring is ignored while an all ones signal is transmitted out to the line interface. 10 framer far-end (remote) line loopback: when framer remote loopback is enabled, the digital data enters the framer interface, however does not enter the framing blocks. the receive digital data from the liu is allowed to pass through the liu decoder/ encoder circuitry before returning to the line interface. 11 framer payload loopback: when framer payload loopback is enabled, the raw data within the receive time slots are looped back to the transmit framer block where the data is re-framed according to the transmit timing.
xrt86vl34 12 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 encode b8zs r/w 0 encode ami or b8zs/hdb3 line code select this bit enables or disables the b8zs/hdb3 encoder on the transmit path. 0 = enables the b8zs encoder. 1 = disables the b8zs encoder. n ote : when b8zs encoder is disabled, ami line code is used. 0 decode ami/b8zs r/w 0 decode ami or b8zs/hdb3 line code select this bit enables or disables the b8zs/hdb3 decoder on the receive path. 0 = enables the b8zs decoder. 1 = disables the b8zs decoder. n ote : when b8zs decoder is disabled, ami line code is received. t able 2: l ine i nterface c ontrol r egister (licr) h ex a ddress : 0 x n101 b it f unction t ype d efault d escription -o peration
xrt86vl34 13 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 86vl34 t able 3: f raming s elect r egister (fsr) h ex a ddress : 0 x n107 b it f unction t ype d efault d escription -o peration 7 g.706 annex b crc-4 calcula - tion enable r/w 0 g.706 annex b crc-4 calculation enable this bit configures the e1 receive framer block to be compliant with itu-t g.706 annex b for crc-to-non-crc interworking detection. if annex b is enabled, g.706 annex b crc-4 multiframe alignment algorithm is imple - mented. if crc-4 alignment is enabled and not achieved in 400msec while the basic frame alignment signal is present, it is assumed that the remote end is a non crc-4 equipment. a crc-to-non-crc interworking interrupt will be generated. the crc-to-non-crc interworking interrupt status can be read from register address 0xnb0a. 0 - configures the receive e1 framer block to not support the ?g.706 annex b? crc-4 multiframe alignment algorithm. 1 - configures the receive e1 framer block to support the ?g.706 annex b? crc-4 multiframe alignment algorithm. 6 transmit crc-4 error r/w 0 transmit crc-4 error this bit is used to force a continuous errored crc pattern in the outbound crc multiframe to be sent on the transmission line. the transmit e1 framer block will implement this error by inverting the value of crc bit (c1). 0 = disables the transmit e1 framer block to transmit errored crc bit. 1 = forces the transmit e1 framer block to transmit continuous errored crc bit. n ote : this bit is ignored if crc multi-framing is disabled.
xrt86vl34 14 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 5-4 cas mf align sel[1:0] r/w 00 cas multiframe alignment declaration algorithm select[1:0] these bits allow the user to select which cas multiframe alignment decla - ration algorithm the receive e1 framer block will employ, according to the table below. n ote : for information on the criteria that the receive e1 framer block uses in order to declare the ?loss of cas multiframe? defect condition, please see register description for the framing control register (fcr - address 0xn10b) t able 3: f raming s elect r egister (fsr) h ex a ddress : 0 x n107 b it f unction t ype d efault d escription -o peration cas mf a lign s el [1:0] cas m ultiframe a lignment d eclaration a lgorithm s elected 00/11 cas multiframe alignment is disabled 01 the ?16-frame? algorithm if this alignment algorithm is selected, then the receive e1 framer block will monitor the 16th timeslot of each incoming e1 frame and will declare cas multiframe align- ment (e.g., clear the loss of cas multiframe? defect) con- dition; anytime that it detects 15 consecutive e1 frames in which bits 1 - 4 (of timeslot 16) do not contain the ?cas multiframe alignment? pattern; which is immediately fol- lowed by an e1 frame that does contain the ?cas multi- frame alignment? pattern. 10 the ?2-frame? (itu-t g.732) algorithm if this alignment algorithm is selected, then the receive e1 framer block will monitor the 16th timeslot of each incoming e1 frame and will declare cas multiframe align- ment (e.g., clear the loss of cas multiframe? defect) con- dition; anytime that it detects a single e1 frame in which bits 1 - 4 (of timeslot 16) do not contain the ?cas multi- frame alignment? pattern; which is immediately followed by an e1 frame that does contain the ?cas multiframe alignment? pattern.
xrt86vl34 15 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 3-2 crc mf align sel[1:0] r/w 00 crc multiframe alignment declaration criteria select [1:0] these two bits allow the user to select which crc-multiframe alignment declaration criteria the receive e1 framer block will employ. the receive e1 framer block will check for crc multiframe alignment by checking the incoming e1 data-stream and determining whether the international bits (bit 1 of timeslot 0) of non-fas frames match the crc multiframe alignment pattern (0,0,1,0,1,1,e1,e2). the table below provides more details on the three different crc multiframe alignment declaration criteria. n ote : for information on the criteria that the receive e1 framer block uses to declare the ?loss of crc multiframe alignment? defect condition, please see register description for the framing control register (fcr - 0xn10b) 1 additional frame check enable - fas r/w 0 additional frame check enable - fas frame alignment declaration this bit permits the user to configure the receive e1 framer block to per - form some ?additional fas frame synchronization checking? prior to declar - ing ?fas frame alignment?. if the user implements this feature, then the receive e1 framer block will perform some more testing on two additional e1 frames, prior to declaring the ?fas frame alignment? condition. 0 - disables this additional fas frame checking. 1 - enables this additional fas frame checking. t able 3: f raming s elect r egister (fsr) h ex a ddress : 0 x n107 b it f unction t ype d efault d escription -o peration crc mf a lign s el [1:0] crc m ultiframe a lignment d eclaration c riteria s elected 00 crc multiframe alignment is disabled 01 crc multiframe alignment is enabled. alignment is declared if at least 1 valid crc multiframe alignment signal (0,0,1,0,1,1,e1,e2) is observed within 8ms. 10 crc multiframe alignment is enabled. alignment is declared if at least 2 valid crc multiframe alignment signals (0,0,1,0,1,1,e1,e2) are observed within 8ms. 11 crc multiframe alignment is enabled. alignment is declared if at least 3 valid crc multiframe alignment signals (0,0,1,0,1,1,e1,e2) are observed within 8ms.
xrt86vl34 16 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 0 fas frame align sel r/w 0 fas alignment declaration algorithm select this bit specifies which algorithm the receive e1 framer block uses in its search for the fas alignment. 0 = selects the fas alignment algorithm 1 1 = selects the fas alignment algorithm 2 fas alignment algorithm 1 if the receive e1 framer block has been configured to use ?fas alignment algorithm # 1", then it will acquire fas alignment by performing the follow - ing three steps: step 1 - the receive e1 framer block begins by searching for the correct 7-bit fas pattern. go to step 2 if found. step 2 - check if the fas is absent in the following frame by verifying that bit 2 of the assumed timeslot 0 of the non-fas frame is a one. go back to step 1 if failed, otherwise, go to step 3. step 3 - check if the fas is present in the assumed timeslot 0 of the third frame. go back to step 1 if failed. after the first three steps (if they all passed), the receive e1 framer block will declare fas in sync if frame check sequence (bit 1 of this register) is disabled. if frame check sequence (bit 1 of this register) is enabled, then the receive e1 framer block will need to verify the correct frame alignment for an additional two frames. fas alignment algorithm 2 if the receive e1 framer block has been configured to support ?fas align - ment algorithm # 2, then it will perform the following 3 steps in order to acquire and declare fas frame alignment with the incoming e1 data- stream. algorithm 2 is similar to algorithm 1 but adds a one-frame hold off time after the second step fails. after the second step fails, it waits for the next assumed fas in the next frame before it begins the new search for the correct fas pattern. step 1 - algorithm 1 begins by searching for the correct 7-bit fas pattern. go to step 2 if found. step 2 - check if the fas is absent in the following frame by verifying that bit 2 of the assumed timeslot 0 of the non-fas frame is a one. go back to step 4 if failed, otherwise, go to step 3. step 3 - check if the fas is present in the assumed timeslot 0 of the third frame. go back to step 1 if failed, otherwise, proceed to check for frame check sequence. step 4 - wait for assumed fas in the next frame, then go back to step 1 after the first three steps (if they all passed), the receive e1 framer block will declare fas in sync if frame check sequence (bit 1 of this register) is disabled. if frame check sequence (bit 1 of this register) is enabled, then the receive e1 framer block will need to verify the correct frame alignment for an additional two frames. t able 3: f raming s elect r egister (fsr) h ex a ddress : 0 x n107 b it f unction t ype d efault d escription -o peration
xrt86vl34 17 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 4: a larm g eneration r egister (agr) h ex a ddress : 0 x n108 b it f unction t ype d efault d escription -o peration 7 transmit auxp pattern r/w 0 transmit auxiliary (auxp) pattern this bit permits the user to command the transmit e1 framer block to transmit the auxp pattern to the remote terminal equipment, as depicted below. 0 - configures the transmit e1 framer block to not transmit the auxp pattern (which is an unframed, repeating 1010... pattern). 1 - configures the transmit e1 framer block to transmit the auxp pattern. the device also supports auxp pattern detection, please read register (address 0xnb0a) for more detail. 6 loss of frame declaration crite - ria r/w 0 loss of frame declaration criteria this bit permits the user to select the ?loss of frame declaration criteria? for the receive e1 framer block, as depicted below. 0 = loss of frame is declared immediately if either crc multiframe align - ment or fas alignment is lost. 1 = loss of frame is declared immediately if fas alignment is lost. if crc multiframe alignment is lost for more than 8ms, e1 receive framer will force a frame search. 5-4 transmit yel and multi-yel[1:0] r/w 00 yellow alarm and multiframe yellow alarm generation [1:0] these bits activate or deactivate the transmission of yellow and multiframe yellow alarm. the yellow alarm and multiframe yellow alarm can be forced to transmit as?1?, or be inserted upon detection of loss of alignment. the decoding of these bits are explained as follows: yel[1:0] y ellow a larm t ransmitted 00/10 yellow alarm and multiframe yellow alarm transmission is disabled. 01 automatic transmission of yellow and cas multiframe yellow alarms are enabled, as described below: 1. whenever the receive e1 framer block declares the lof (loss of fas framing) defect condition: the corresponding transmit e1 framer block will automati- cally transmit the yellow alarm indicator (by setting bit 3 of time-slot 0, within the non-fas frames) to 1" whenever (and for the duration that) the receive e1 framer block declares the lof defect condition. 2. whenever the receive e1 framer block declares the ?loss of cas multiframe alignment? defect condition: the corresponding transmit e1 framer block will automati- cally transmit the cas multiframe yellow alarm indicator (by setting bit 6 within ?frame 0" of time-slot 16) to ?1? when- ever (and for the duration that) the receive e1 framer block declares the loss of cas multiframe defect condition. 11 force transmission of yellow and multiframe yellow alarm both yellow and multiframe yellow alarm are transmitted as ?1? when this is enabled.
xrt86vl34 18 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3-2 transmit ais pat - tern select[1:0] r/w 00 types of ais pattern generation select these bits permit the user to do the following. a. to select the type of ais pattern that the transmit e1 framer block will transmit. b. to force (via software-control) the transmission of the ?selected? ais pattern. n ote : for ?normal? operation, the user should set these bits to ?[0, 0]?. 1-0 ais defect decla - ration criteria[1:0] r/w 00 ais defect declaration criteria[1:0]: these bits permit the user to specify the types of ais patterns that the receive e1 framer block must detect before it will declare the ais defect condition. n ote : in revision c of xrt86vl34, receive e1 framer will always monitor ais16 condition and report the state and interrupt status without having to enable these two bits. ais16 alarm state and interrupt status can be read from register 0xnb12, 0xnb13. t able 4: a larm g eneration r egister (agr) h ex a ddress : 0 x n108 b it f unction t ype d efault d escription -o peration aisg[1:0] t ypes of ais p attern t ransmitted 00 transmission of ais indicator is disabled the transmit e1 framer block will transmit ?nor- mal? e1 traffic to the remote terminal equipment. 01 unframed ais alarm transmit e1 framer block will transmit an unframed all ones pattern, as an ais pattern. 10 the ais-16 pattern in this case, time-slot 16 (within each outbound e1 frame) will be set to an ?all ones? pattern. 11 framed ais alarm transmit e1 framer block will transmit a framed all ones pattern, as an ais pattern. aisd[1:0] ais defect declaration criteria 00 ais defect condition will not be declared. 01 receive e1 framer block will detect both unframed and framed ais pattern 10 receive e1 framer block will detect ais16 (time slot 16 ais) pattern*. 11 receive e1 framer block will detect only framed ais pattern
xrt86vl34 19 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 5: s ynchronization mux r egister (smr) h ex a ddress : 0 x n109 b it f unction t ype d efault d escription -o peration 7-6 e bit source sel[1:0] r/w 00 source for e bits [1:0] these bits permit the user to specify the source of the e-bits, within each outbound e1 frame, as depicted below. n ote : this bit is only active if the transmit e1 framer block has been configured to internally generate and insert the various framing alignment bits within the outbound e1 data-stream. in other words, whenever the ?framing alignment pattern source select? bit (within bit 0 of this register) is set to ?0?. 5 reserved - - reserved esrc[1:0] s ource for e- bits 00 the corresponding receive e1 framer block: in this case, the e-bits will be used to indicate whether the receive e1 framer block has detected a crc error within the most recently received sub-multiframe. the receive e1 framer will indicate a received errored sub-multiframe by setting the binary state of e bit from ?1? to ?0? for each errored sub-multi- frame. 01 all e bits (within the outbound e1 data-stream) are set to ?0?. 10 all e bits (within the outbound e1 data-stream) are set to ?1?. 11 the outgoing e bits will be used to carry data link information.
xrt86vl34 20 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 4 transmit frame sync select r/w 0 transmit frame sync select this bit permits the user to configure the system-side terminal equipment or the e1 transmit framer to dictate whenever the trans - mit e1 framer block will initiate its generation and transmission of the very next e1 frame. if the system side controls, then all of the fol - lowing will be true. 1. the corresponding txsync_n and txmsync_n pins will function as input pins. 2. the transmit e1 framer block will initiate its generation of a new e1 frame whenever it samples the corresponding ?txsync_n? input pin ?high? (via the txserclk_n input clock signal). 3. the transmit e1 framer block will initiate its generation of a new crc multiframe whenever it samples the corresponding ?txmsync_n? input pin ?high?. this bit can also be used to select the direction of the transmit single frame boundary (txsync) and multi-frame boundary (txmsync) depending on whether txserclk is chosen as the timing source for the transmit section of the framer. (css[1:0] = 01 in register 0xn100) if txserclk is chosen as the timing source: 0 = configures txsync and txmsync as inputs. (system side controls) 1 = configures txsync and txmsync as outputs. (chip controls) if either recovered line clock, mclk pll is chosen as the tim - ing source: 0 = configures txsync and txmsync as outputs. (chip controls) 1 = configures txsync and txmsync as inputs. (system side controls) n ote : txserclk is chosen as the transmit clock if css[1:0] of the clock select register (register address: 0xn100) is set to b01. recovered clock is chosen as the transmit clock if css[1:0] is set to b00 or b11; internal clock is chosen as the transmit clock if css[1:0] is set to b10. 3-2 data link source select [1:0] r/w 00 data link source select these bits are used to specify the source of the data link bits that will be inserted in the outbound e1 frames. the table below describes the three different sources from which the data link bits can be inserted. t able 5: s ynchronization mux r egister (smr) h ex a ddress : 0 x n109 b it f unction t ype d efault d escription -o peration dlsrc[1:0] s ource of d ata l ink bits 00/11 txser input - the transmit serial input from the transmit payload data input block will be the source for data link bits 01 transmit hdlc controller - the transmit hdlc controller will generate either bos (bit oriented signaling) or mos (message oriented signaling) messages which will be inserted into the data link bits in the outbound e1frames. 10 txoh input - the transmit overhead data input port will be the source for the data link bits.
xrt86vl34 21 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 crc-4 bits source sel r/w 0 crc-4 bits source select this bit permits the user to specify the source of the crc-4 bits, within the outbound e1 data-stream, as depicted below. 0 - configures the transmit e1 framer block to internally compute and insert the crc-4 bits within the outbound e1 data-stream. 1 - configures the transmit e1 framer block to externally accept data from the txser_n input pin, and to insert this data into the crc- 4 bits within the outbound e1 data-stream. n ote : this bit is ignored if crc multiframe alignment is disabled 0 framing alignment pat - tern source select r/w 0 framing alignment pattern source select this bit permits the user to specify the source of the various ?fram - ing alignment? bits (which includes the fas bits, the crc multiframe alignment bits, the e and a bits). 0 - configures the transmit e1 framer block to internally generate and insert these various framing alignment bits into the outbound e1 data-stream. 1 - configures the transmit e1 framer block to externally accept data from the txser_n input pin, and to insert this data into the fas, crc multiframe, e and a bits within the outbound e1 data-stream. n ote : users can specify the source for e-bits in register bits 6-7 within this register if transmit e1 framer is configured to internally generate the various framing alignment bits (i.e. this bit set to?0?). t able 5: s ynchronization mux r egister (smr) h ex a ddress : 0 x n109 b it f unction t ype d efault d escription -o peration
xrt86vl34 22 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 6: t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x n10a b it f unction t ype d efault d escription -o peration 7 txsa8enb r/w 0 transmit sa8 enable this bit specifies if the sa8 bits (bit 7 within timeslot 0 of non-fas frames) will be involved in the transmission of data link information. 0 = sa8 will not be used to transport data link information. sa8 bits will be set to ?1? within the outbound e1 data-stream if the sa8 bits are inserted from the trans - mit serial input. 1 = sa8 will be used to transport data link information. n ote : sa8 bits can be inserted from either the transmit serial input or register depending on the transmit sa select register (register address: 0xn130) setting. the data link interface uses sa8 bits for transmission only if data link source is from hdlc controller (dlsrc = b01 from register 0xn109) and if sa8 bits are inserted from the transmit serial input (txsa8sel = 0 from register 0xn130). 6 txsa7enb r/w 0 transmit sa7 enable this bit specifies if the sa7 bits (bit 6 within timeslot 0 of non-fas frames) will be involved in the transmission of data link information. 0 = sa7 will not be used to transport data link information. sa7 bits will be set to ?1? within the outbound e1 data-stream if the sa7 bits are inserted from the trans - mit serial input. 1 = sa7 will be used to transport data link information. n ote : sa7 bits can be inserted from either the transmit serial input or register depending on the transmit sa select register (register address: 0xn130) setting. the data link interface uses sa8 bits for transmission only if data link source is from hdlc controller (dlsrc = b01 from register 0xn109) and if sa7 bits are inserted from the transmit serial input (txsa7sel = 0 from register 0xn130). 5 txsa6enb r/w 0 transmit sa6 enable this bit specifies if the sa6 bits (bit 5 within timeslot 0 of non-fas frames) will be involved in the transmission of data link information. 0 = sa6 will not be used to transport data link information. sa6 bits will be set to ?1? within the outbound e1 data-stream if the sa6 bits are inserted from the trans - mit serial input. 1 = sa6 will be used to transport data link information. n ote : sa6 bits can be inserted from either the transmit serial input or register depending on the transmit sa select register (register address: 0xn130) setting. the data link interface uses sa6 bits for transmission only if data link source is from hdlc controller (dlsrc = b01 from register 0xn109) and if sa6 bits are inserted from the transmit serial input (txsa6sel = 0 from register 0xn130). 4 txsa5enb r/w 0 transmit sa5 enable this bit specifies if the sa5 bits (bit 4 within timeslot 0 of non-fas frames) will be involved in the transmission of data link information. 0 = sa5 will not be used to transport data link information. sa5 bits will be set to ?1? within the outbound e1 data-stream if the sa5 bits are inserted from the trans - mit serial input. 1 = sa5 will be used to transport data link information. sa5 bits can be inserted from either the transmit serial input or register depending on the transmit sa select register (register address: 0xn130) setting. the data link interface uses sa5 bits for transmission only if data link source is from hdlc controller (dlsrc = b01 from register 0xn109) and if sa5 bits are inserted from the transmit serial input (txsa5sel = 0 from register 0xn130).
xrt86vl34 23 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 3 txsa4enb r/w 0 transmit sa4 enable this bit specifies if the sa4 bits (bit 3 within timeslot 0 of non-fas frames) will be involved in the transmission of data link information. 0 = sa4 will not be used to transport data link information. sa4 bits will be set to ?1? within the outbound e1 data-stream if the sa4 bits are inserted from the trans - mit serial input. 1 = sa4 will be used to transport data link information. sa4 bits can be inserted from either the transmit serial input or register depending on the transmit sa select register (register address: 0xn130) setting. the data link interface uses sa4 bits for transmission only if data link source is from hdlc controller (dlsrc = b01 from register 0xn109) and if sa4 bits are inserted from the transmit serial input (txsa5sel = 0 from register 0xn130). t able 6: t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x n10a b it f unction t ype d efault d escription -o peration
xrt86vl34 24 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 2-0 txsigdl[2:0] r/w 000 transmit signaling and data link select[2:0]: these bits are used to specify the source for d/e channel, national bits in timeslot 0 of the non-fas frames, and timeslot 16 of the outbound e1 frames. the table below presents the settings of these three bits in detail. t able 6: t ransmit s ignaling and d ata l ink s elect r egister (tsdlsr) h ex a ddress :0 x n10a b it f unction t ype d efault d escription -o peration t x sigdl [2:0] s ource of d/e c hannel s ource of n ational b its s ource of t ime s lot 16 000 txfrtd_n or txser_n input pin data link txser_n input pin 001 txfrtd_n or txser_n input pin data link cas signaling is enabled. time slot 16 can be inserted from any of the fo l- lowing: ? txser_n input pin ? tscr register (0xn340-0xn35f) ? txoh_n input pin on time slot 1 6 only ? txsig_n input pin on every slot 010 txfrtd_n or txser_n input pin forced to all ones txser_n input pin or txsig_n input pin on time slot 16 on ly 011 txfrtd_n or txser_n input pin forced to all ones cas signaling is enabled. time slot 16 can be inserted from any of the fo l- lowing: ? txser_n input pin ? tscr register (0xn340-0xn35f) ? txoh_n input pin on time slot 1 6 only ? txsig_n input pin on every slot 100 txsig_n or txser_n input pin data link txser_n input pin 101/ 110/ 111 not used not used not used
xrt86vl34 25 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 7: f raming c ontrol r egister (fcr) h ex a ddress : 0 x n10b b it f unction t ype d efault d escription -o peration 7 reframe r/w 0 force reframe a ?0? to ?1? transition will force the receive e1 framer to restart the syn - chronization process. this bit field is automatically cleared (set to 0) after frame synchronization is reached. 6-5 loss of cas mf align_sel [1:0] r/w 10 loss of cas multiframe alignment defect declaration criteria select [1:0] these two bits permit the user to select the ?loss of cas multiframe alignment? defect declaration criteria. loss of cas multiframe align - ment defect is declared based on the number of consecutive cas mul - tiframes with multiframe alignment signal received in error as indicated in the table below . n ote : these bits are active only if cas multiframe alignment is enabled. 4-3 loss of crc multi - frame align_sel[1:0] r/w 00 loss of crc-4 multiframe alignment defect declaration criteria select [1:0] these two bits permit the user to select the ?loss of crc-4 multiframe alignment? defect declaration criteria for the channel. the following table presents the different crc-4 multiframe algorithms in terms of the number of consecutive erred crc-4 multiframe alignments that the e1 receiver framer will receive before it declares the ?loss of crc-4 multiframe alignment? defect condition. n ote : these bits are only active if crc multiframe alignment is enabled. if crc multiframe alignment is not found in 8ms, the e1 receive framer will restart the synchronization process. n ote : tbr-4 standard is enabled by writing to 0xn112, bit 6. casc[1:0] l oss of cas m ultiframe a lignment d eclaration c riteria 00 2 consecutive cas multiframes 01 3 consecutive cas multiframes 10 4 consecutive cas multiframes 11 8 consecutive cas multiframes crcc[1:0] l oss of crc-4 m ultiframe a lignment d eclaration c riteria 00 4 consecutive crc-4 multiframes alignment 01 2 consecutive crc-4 multiframes alignment 10 8 consecutive crc-4 multiframes alignment 11 if tbr-4 standard is enabled*: 4 consecutive crc-4 multiframe alignment or 915 or more crc-4 errors if tbr-4 standard is disabled*: 915 or more crc-4 errors
xrt86vl34 26 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 2-0 fasc [2:0] r/w 011 loss of fas alignment defect declaration criteria select [2:0] these bits permit the user to specify the loss of fas alignment defect declaration criteria. the following table presents the different fas alignment algorithms in terms of the number of consecutive erred fas patterns within a multiframe that the e1 receiver framer will receive before it declares the ?loss of fas alignment? defect conditions n ote : loss of fas alignment will force the e1 receive framer to declare the loss of cas multiframe alignment and loss of crc multiframe alignment. t able 7: f raming c ontrol r egister (fcr) h ex a ddress : 0 x n10b b it f unction t ype d efault d escription -o peration fasc[2:0] l oss of fas a lignment d eclaration c riteria 000 setting these bits to ?b000? is illegal. do not use this configuration. 001 1 fas alignment pattern 010 2 consecutive fas alignment patterns 011 3 consecutive fas alignment patterns 100 4 consecutive fas alignment patterns 101 5 consecutive fas alignment patterns 110 6 consecutive fas alignment patterns 111 7 consecutive fas alignment patterns
xrt86vl34 27 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 8: r eceive s ignaling & d ata l ink s elect r egister (rsdlsr) h ex a ddress : 0 x n10c b it f unction t ype d efault d escription -o peration 7 rxsa8enb r/w 0 receive sa8 enable this bit is used to specify whether or not sa 8 (bit 7 within timeslot 0 of non-fas frames) will be used to receive data link information 0 = sa8 is not used to receive data link information 1 = sa8 is used to receive data link information n ote : this bit is valid only if the rxsigdl[2:0] = ?000?, ?001?, or ?100?. (the national bits have been configured to receive data link bits). 6 rxsa7enb r/w 0 receive sa7 enable this bit is used to specify whether or not sa 7 (bit 6 within timeslot 0 of non-fas frames) will be used to receive data link information 0 = sa7 is not used to receive data link information 1 = sa7 is used to receive data link information n ote : this bit is valid only if the rxsigdl[2:0] = ?000?, ?001?, or ?100?. (the national bits have been configured to receive data link bits). 5 rxsa6enb r/w 0 receive sa6 enable this bit is used to specify whether or not sa 6 (bit 5 within timeslot 0 of non-fas frames) will be used to receive data link information 0 = sa6 is not used to receive data link information 1 = sa6 is used to receive data link information n ote : this bit is valid only if the rxsigdl[2:0] = ?000?, ?001?, or ?100?. (the national bits have been configured to receive data link bits). 4 rxsa5enb r/w 0 receive sa5 enable this bit is used to specify whether or not sa 5 (bit 4 within timeslot 0 of non-fas frames) will be used to receive data link information 0 = sa5 is not used to receive data link information 1 = sa5 is used to receive data link information n ote : this bit is valid only if the rxsigdl[2:0] = ?000?, ?001?, or ?100?. (the national bits have been configured to receive data link bits). 3 rxsa4enb r/w 0 receive sa4 enable this bit is used to specify whether or not sa 4 (bit 3 within timeslot 0 of non-fas frames) will be used to receive data link information 0 = sa4 is not used to receive data link information 1 = sa4 is used to receive data link information n ote : this bit is valid only if the rxsigdl[2:0] = ?000?, ?001?, or ?100?. (the national bits have been configured to receive data link bits).
xrt86vl34 28 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 2-0 rxsigdl[2:0] r/w 000 receive signaling and datalink select[2:0]: these bits specify the destination for the data that is to be extracted via d/e channel, national bits in timeslot 0 of the non-fas frames, and timeslot 16 in the outbound frames. the table below presents the settings of these three rxsigdl bits in detail. t able 8: r eceive s ignaling & d ata l ink s elect r egister (rsdlsr) h ex a ddress : 0 x n10c b it f unction t ype d efault d escription -o peration r x sigdl [2:0] d/e c hannel n ational b its t ime s lot 16 000 rxfrtd_n or the rxser_n output pin data link rxser_n output pin 001 rxfrtd_n or the rxser_n output pin data link cas signaling is enabled. time slot 16 can be extracted to any of the following: ? rxser_n output pin ? rsar register (0xn500-0xn51f) ? rxoh_n output pin on time slot 16 only ? rxsig_n output pin on every time slot 010 rxfrtd_n or the rxser_n output pin data link forced to all ones time slot 16 can be extracted to any of the following: ? rxser_n output pin ? rsar register (0xn500-0xn51f) ? rxoh_n output pin on time slot 16 only ? rxsig_n output pin on time slot 16 only 011 rxfrtd_n or the rxser_n output pin data link forced to all ones cas signaling is enabled. time slot 16 can be extracted to any of the following: ? rxser_n output pin ? rsar register (0xn500-0xn51f) ? rxoh_n output pin on time slot 16 only rxsig_n output pin on every time slot 100 rxsig_n or the rxser_n output pin data link rxser_n output pin 101/110/ 111 not used not used not used
xrt86vl34 29 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 9: r eceive s ignaling c hange r egister 0 (rscr 0) h ex a ddress : 0 x n10d b it f unction t ype d efault d escription -o peration 7 ch. 0 rur 0 these bits indicate whether the channel associated signaling data, associated with time-slots 0 through 7 within the incoming e1 data- stream, has changed since the last read of this register, as depicted below. 0 - cas data (for time-slots 0 through 7) has not changed since the last read of this register. 1 - cas data (for time-slots 0 through 7) has changed since the last read of this register. n otes : 1. bit 7 (time-slot 0) is not active, since it carries the fas and national bits. n ote : 2. this register is only active if the incoming e1 data-stream is using channel associated signaling. 6 ch. 1 rur 0 5 ch.2 rur 0 4 ch.3 rur 0 3 ch.4 rur 0 2 ch.5 rur 0 1 ch.6 rur 0 0 ch.7 rur 0 t able 10: r eceive s ignaling c hange r egister 1 (rscr 1) h ex a ddress : 0 x n10e b it f unction t ype d efault d escription -o peration 7 ch.8 rur 0 these bits indicate whether the channel associated signaling data, associated with time-slots 8 through 15 within the incoming e1 data- stream, has changed since the last read of this register, as depicted below. 0 - cas data (for time-slots 8 through 15) has not changed since the last read of this register. 1 - cas data (for time-slots 8 through 15) has changed since the last read of this register. n ote : this register is only active if the incoming e1 data-stream is using channel associated signaling. 6 ch.9 rur 0 5 ch.10 rur 0 4 ch.11 rur 0 3 ch.12 rur 0 2 ch.13 rur 0 1 ch.14 rur 0 0 ch.15 rur 0 t able 11: r eceive s ignaling c hange r egister 2 (rscr 2) h ex a ddress : 0 x n10f b it f unction t ype d efault d escription -o peration 7 ch.16 rur 0 these bits indicate whether the channel associated signaling data, associated with time-slots 16 through 23 within the incoming e1 data- stream, has changed since the last read of this register, as depicted below. 0 - cas data (for time-slots 16 through 23) has not changed since the last read of this register. 1 - cas data (for time-slots 16 through 23) has changed since the last read of this register. n ote : this register is only active if the incoming e1 data-stream is using channel associated signaling. 6 ch.17 rur 0 5 ch.18 rur 0 4 ch.19 rur 0 3 ch.20 rur 0 2 ch.21 rur 0 1 ch.22 rur 0 0 ch.23 rur 0
xrt86vl34 30 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 12: r eceive s ignaling c hange r egister 3 (rscr 3) h ex a ddress : 0 x n110 b it f unction t ype d efault d escription -o peration 7 ch.24 rur 0 these bits indicate whether the channel associated signaling data, associated with time-slots 24 through 31 within the incoming e1 data-stream, has changed since the last read of this register, as depicted below. 0 - cas data (for time-slots 24 through 31) has not changed since the last read of this register. 1 - cas data (for time-slots 24 through 31) has changed since the last read of this register. n ote : this register is only active if the incoming e1 data-stream is using channel associated signaling. 6 ch.25 rur 0 5 ch.26 rur 0 4 ch.27 rur 0 3 ch.28 rur 0 2 ch.29 rur 0 1 ch.30 rur 0 0 ch.31 rur 0
xrt86vl34 31 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 13: r eceive n ational b its r egister (rnbr) h ex a ddress : 0 x n111 b it f unction t ype d efault d escription -o peration 7 si_fas ro x received international bit - fas frame this read only bit contains the value of the international bit (e.g., the si bit) in the most recently received fas frame. 6 si_nonfas ro x received international bit - non fas frame this read only bit contains the value of the international bit (e.g., the si bit) in the most recently received non-fas frame 5 r_alarm ro x received a bit - non fas frame this read only bit contains the value in the remote alarm indication bit (a bit, or bit 3 of non-fas frame) within the most recently received non-fas frame. 4 sa4 ro x received national bits these read only bits contain the values of the national bits (sa4- sa8) within the most recently received non-fas frame. 3 sa5 ro x 2 sa6 ro x 1 sa7 ro x 0 sa8 ro x
xrt86vl34 32 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 14: r eceive e xtra b its r egister (rebr) h ex a ddress : 0 x n112 b it f unction t ype d efault d escription -o peration 7 in-frame ro 0 in frame state: this read-only bit indicates whether the receive e1 framer block is currently declaring the ?in-frame? condition with the incoming e1 data- stream. 0 - indicates that the receive e1 framer block is currently declaring the lof (loss of frame) defect condition. 1 - indicates that the receive e1 framer block is currently declaring itself to be in the ?in-frame? condition. 6 tbr4_std r/w 0 tbr4 standard setting this bit will force the xrt86vl34 to be compliant with the tbr-4 standard for ?loss of crc-4 multiframe alignment criteria?. 0 - backward compatible with xrt86l38 for loss of crc-4 multiframe criteria. when crcc[1:0] (from register 0xn10b) is set to?11?, loss of crc-4 multiframe alignment will declare if 915 or more crc-4 errors have been detected in 1 second. 1 - ?tbr-4 compliant? loss of crc-4 multiframe alignment criteria - when crcc[1:0] (from register 0xn10b) is set to?11?, loss of crc-4 mul - tiframe alignment will declare if 4 consecutive crc-4 multiframe align - ment have been received in error or if 915 or more crc-4 errors have been detected in 1 second. 5-4 reserved - - reserved 3 ex1 ro x extra bit 1 this read only bit field indicates the value of the most recently received extra bit value (bit 5 within timeslot 16 of frame 0 of the signal - ing multiframe). n ote : this bit only has meaning if the framer is using channel associated signaling. 2 alarmfe ro x cas multi-frame yellow alarm this read only bit field indicates the value of the most recently received cas multiframe yellow alarm bit (bit 6 within timeslot 16 of frame 0 of the signaling multiframe). 0 = indicates that the e1 receive framer block is not receiving the cas multiframe yellow alarm. 1 = indicates that the e1 receive framer block is currently receiving the cas multiframe yellow alarm. n ote : this bit only has meaning if the framer is using channel associated signaling.
xrt86vl34 33 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 ex2 ro x extra bit 2 this read only bit field indicates the value of the most recently received extra bit value (bit 7 within timeslot 16 of frame 0 of the signal - ing multiframe). n ote : this bit only has meaning if the framer is using channel associated signaling. 0 ex3 ro x extra bit 3 this read only bit field indicates the value of the most recently received extra bit value (bit 8 within timeslot 16 of frame 0 of the signal - ing multiframe). n ote : this bit only has meaning if the framer is using channel associated signaling. t able 14: r eceive e xtra b its r egister (rebr) h ex a ddress : 0 x n112 b it f unction t ype d efault d escription -o peration
xrt86vl34 34 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 15: d ata l ink c ontrol r egister (dlcr1) h ex a ddress : 0 x n113 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved. please set this bit to?0? for normal operation. 6 mos abort disable r/w 0 mos abort disable: this bit permits the user to either enable or disable the ?automatic mos abort? feature within transmit hdlc controller # 1. if the user enables this feature, then transmit hdlc controller block # 1 will automatically transmit the abort sequence (e.g., a zero fol - lowed by a string of 7 consecutive ?1s?) whenever it abruptly transi - tions from transmitting a mos type of message, to transmitting a bos type of message. if the user disables this feature, then the transmit hdlc controller block # 1 will not transmit the abort sequence, whenever it abruptly transitions from transmitting a mos-type of message to transmitting a bos-type of message. 0 - enables the ?automatic mos abort? feature 1 - disables the ?automatic mos abort? feature 5 rx_fcs_dis r/w 0 receive frame check sequence (fcs) verification enable/dis - able this bit permits the user to configure the receive hdlc controller block # 1 to compute and verify the fcs value within each incoming lapd message frame. 0 - enables fcs verification 1 - disables fcs verification 4 autorx r/w 0 auto receive lapd message this bit configures the receive hdlc controller block #1 to discard any incoming bos or lapd message frame that exactly match which is currently stored in the receive hdlc1 buffer. 0 = disables this ?auto discard? feature 1 = enables this ?auto discard? feature. 3 tx_abort r/w 0 transmit abort this bit configures the transmit hdlc controller block #1 to trans - mit an abort sequence (string of 7 or more consecutive 1?s) to the remote terminal. 0 - configures the transmit hdlc controller block # 1 to function normally (e.g., not transmit the abort sequence). 1 - configures the transmit hdlc controller block # 1 to transmit the abort sequence.
xrt86vl34 35 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 tx_idle r/w 0 transmit idle (flag sequence byte) this bit configures the transmit hdlc controller block #1 to uncon - ditionally transmit a repeating string of flag sequence octets (0x7e) in the data link channel to the remote terminal. in normal condi - tions, the transmit hdlc controller block will repeatedly transmit the flag sequence octet whenever there is no mos message to transmit to the remote terminal equipment. however, if the user invokes this ?transmit idle sequence? feature, then the transmit hdlc controller block will unconditionally transmit a repeat - ing stream of the flag sequence octet (thereby overwriting all out - bound mos data-link messages). 0 - configures the transmit hdlc controller block # 1 to transmit data-link information in a ?normal? manner. 1 - configures the transmit hdlc controller block # 1 to transmit a repeating string of flag sequence octets (0x7e). n ote : this bit is ignored if the transmit hdlc1 controller is operating in the bos mode - bit 0 (mos/bos) within this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with frame check sequence (fcs) this bit permits the user to configure the transmit hdlc controller block # 1 to compute and append fcs octets to the ?back-end? of each outbound mos data-link message. 0 - configures the transmit hdlc controller block # 1 to not com - pute and append the fcs octets to the back-end of each outbound mos data-link message. 1 - configures the transmit hdlc controller block # 1 to com - pute and append the fcs octets to the back-end of each outbound mos data-link message. n ote : this bit is ignored if the transmit hdlc1 controller has been configured to operate in the bos mode - bit 0 (mos/bos) within this register is set to 0. 0 mos/ bos r/w 0 message oriented signaling/bit oriented signaling send this bit permits the user to enable lapd transmission through hdlc controller block # 1 using either bos (bit-oriented signaling) or mos (message-oriented signaling) frames. 0 - transmit hdlc controller block # 1 bos message send. 1 - transmit hdlc controller block # 1 mos message send. n ote : this is not an enable bit. this bit must be set to "0" each time a bos is to be sent. t able 15: d ata l ink c ontrol r egister (dlcr1) h ex a ddress : 0 x n113 b it f unction t ype d efault d escription -o peration
xrt86vl34 36 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 16: t ransmit d ata l ink b yte c ount r egister (tdlbcr1) h ex a ddress : 0 x n114 b it f unction t ype d efault d escription -o peration 7 txhdlc1 bufavail/ bufsel r/w 0 transmit hdlc1 buffer available/buffer select this bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below. if the user is writing data into this register bit: 0 - configures the transmit hdlc1 controller to read out and trans - mit the data, residing within ?transmit hdlc1 buffer # 0", via the data link channel to the remote terminal equipment. 1 - configures the transmit hdlc1 controller to read out and trans - mit the data, residing within the ?transmit hdlc1 buffer #1?, via the data link channel to the remote terminal equipment. if the user is reading data from this register bit: 0 - indicates that ?transmit hdlc1 buffer # 0" is the next available buffer. in this case, if the user wishes to write in the contents of a new ?outbound? data link message into the transmit hdlc1 mes - sage buffer, he/she should proceed to write this message into ?transmit hdlc1 buffer # 0" - address location: 0xn600. 1 - indicates that ?transmit hdlc1 buffer # 1" is the next available buffer. in this case, if the user wishes to write in the contents of a new ?outbound? data link message into the transmit hdlc1 mes - sage buffer, he/she should proceed to write this message into ?transmit hdlc1 buffer # 1" - address location: 0xn700. n ote : if one of these transmit hdlc1 buffers contain a message which has yet to be completely read-in and processed for transmission by the transmit hdlc1 controller, then this bit will automatically reflect the value corresponding to the next available buffer when it is read. changing this bit to the in- use buffer is not permitted. 6-0 tdlbc[6:0] r/w 0000000 transmit hdlc1 message - byte count the exact function of these bits depends on whether the transmit hdlc 1 controller is configured to transmit mos or bos messages to the remote terminal equipment. in bos mode: these bit fields contain the number of repetitions the bos message must be transmitted before the transmit hdlc1 controller gener - ates the transmit end of transfer (txeot) interrupt and halts trans - mission. if these fields are set to 00000000, then the bos message will be transmitted for an indefinite number of times. in mos mode: these bit fields contain the length, in number of octets, of the mes - sage to be transmitted. the length of mos message specified in these bits include header bytes such as the sapi, tei, control field, however, it does not include the fcs bytes.
xrt86vl34 37 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 17: r eceive d ata l ink b yte c ount r egister (rdlbcr1) h ex a ddress : 0 x n115 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc1 buffer-pointer this bit identifies which receive hdlc1 buffer contains the most recently received hdlc1 message. 0 - indicates that receive hdlc1 buffer # 0 contains the contents of the most recently received hdlc message. 1 - indicates that receive hdlc1 buffer # 1 contains the contents of the most recently received hdlc message. 6-0 rdlbc[6:0] r/w 0000000 receive hdlc message - byte count the exact function of these bits depends on whether the receive hdlc controller block #1 is configured to receive mos or bos messages. in bos mode: these seven bits contain the number of repetitions the bos mes - sage must be received before the receive hdlc1 controller gener - ates the receive end of transfer (rxeot) interrupt. if these bits are set to ?0000000?, the message will be received indefinitely and no receive end of transfer (rxeot) interrupt will be generated. in mos mode: these seven bits contain the size in bytes of the hdlc1 message that has been received and written into the receive hdlc buffer. the length of mos message shown in these bits include header bytes such as the sapi, tei, control field, and the fcs bytes.
xrt86vl34 38 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 18: s lip b uffer c ontrol r egister (sbcr) h ex a ddress : 0 x n116 b it f unction t ype d efault d escription -o peration 7 txsb_isfifo r/w 0 transmit slip buffer mode this bit permits the user to configure the transmit slip buffer to function as either ?slip-buffer? mode, or as a ?fifo?, as depicted below. 0 - configures the transmit slip buffer to function as a ?slip-buffer?. 1 - configures the transmit slip buffer to function as a ?fifo?. n ote : transmit slip buffer is only used in high-speed or multiplexed mode where txserclkn must be configured as inputs only. users must make sure that the ?transmit direction? timing (i.e. txmsync) and the txserclk input clock signal are synchronous to prevent any transmit slips from occurring. n ote : the data latency is dictated by fifo latency in the fifo latency register (register 0xn117). 6-5 reserved - - reserved 4 sb_forcesf r/w 0 force signaling freeze this bit permits the user to freeze any signaling update on the rxsign output pin as well as the receive signaling array register -rsar (0xn500-0xn51f) until this bit is cleared. 0 = signaling on rxsig and rsar is updated immediately. 1 = signaling on rxsig and rsar is not updated until this bit is set to ?0?. 3 sb_sfenb r/w 0 signal freeze enable upon buffer slips this bit enables signaling freeze for one multiframe after the receive buffer slips. if signaling freeze is enabled, then the ?receive channel? will freeze all signaling updates on rxsig pin and rsar (0xn500-0xn51f) for at least ?one-multiframe? period, after a ?slip-event? has been detected within the ?receive slip buffer?. 0 = disables signaling freeze for one multi-frame after receive buffer slips. 1 = enables signaling freeze for one multi-frame after receive buffer slips. 2 sb_sdir r/w 1 slip buffer (rxsync) direction select this bit permits user to select the direction of the receive frame boundary (rxsync) signal if the receive buffer is enabled. (i.e. sb_enb[1:0] = 01 or 10). if slip buffer is bypassed, rxsync is always an output pin. 0 = selects the rxsync signal as an output 1 = selects the rxsync signal as an input
xrt86vl34 39 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1-0 sb_enb[1:0] r/w 01 receive slip buffer mode select these bits select modes of operation for the receive slip buffer. these two bits also select the direction of rxserclk and rxsync in base clock rate (2.048mhz). the following table shows the corresponding slip buffer modes as well as the direction of the rxsync/rxserclk according to the setting of these two bits. n ote : if the user configures the receive slip buffer to operate in the ?fifo mode?, then the user must make sure that the rxserclk input pin is synchronized to the recovered clock signal for this particular channel. t able 19: fifo l atency r egister (ffolr) h ex a ddress : 0 x n117 b it f unction t ype d efault d escription -o peration 7-5 reserved - - reserved 4-0 rx slip buffer fifo latency[4:0] r/w 00100 receive slip buffer fifo latency[4:0]: these bits permit the user to specify the ?receive data? latency (in terms of rxserclk_n clock periods), whenever the receive slip buffer has been configured to operate in the ?fifo? mode. n ote : these bits are only active if the receive slip buffer has been configured to operate in the fifo mode. t able 18: s lip b uffer c ontrol r egister (sbcr) h ex a ddress : 0 x n116 b it f unction t ype d efault d escription -o peration sb_enb [1:0] r eceive s lip b uffer m ode s elect d irection of r x serclk d irection of r x sync 00/11 receive slip buffer is bypassed output output 01 slip buffer mode input depends on the setting of sb_sdir (bit 2 of this register) if sb_sdir = 0: rxsync = output if sb_sdir = 1: rxsync = input 10 fifo mode. fifo data latency can be programmed by the 'fifo latency register' (address = 0xn117). input depends on the setting of sb_sdir (bit 2 of this register) if sb_sdir = 0: rxsync = output if sb_sdir = 1: rxsync = input
xrt86vl34 40 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 20: dma 0 (w rite ) c onfiguration r egister (d0wcr) h ex a ddress : 0 x n118 b it f unction t ype d efault d escription -o peration 7 dma0 rst r/w 0 dma_0 reset this bit resets the transmit dma (write) channel 0. 0 = normal operation. 1 = a zero to one transition resets the transmit dma (write) channel 0. 6 dma0 enb r/w 0 dma_0 enable this bit enables the transmit dma_0 (write) interface. after a transmit dma is enabled, dma transfers are only requested when the transmit buffer status bits indicate that there is space for a complete message or cell. the dma write channel is used by the external dma controller to transfer data from the external memory to the hdlc buffers within the e1 framer. the dma write cycle starts by e1 framer asserting the dma request ( req0) ?low?, then the external dma controller should drive the dma acknowledge ( ack0) ?low? to indicate that it is ready to start the transfer. the external dma controller should place new data on the microprocessor data bus each time the write signal is strobed low if the wr is configured as a write strobe. if wr is configured as a direction signal, then the external dma controller would place new data on the microprocessor data bus each time the read signal (rd) is strobed low. 0 = disables the transmit dma_0 (write) interface 1 = enables the transmit dma_0 (write) interface 5 wr type r/w 0 write type select this bit selects the function of the wr signal. 0 = wr functions as a direction signal (indicates whether the current bus cycle is a read or write operation) and rd functions as a data strobe signal. 1 = wr functions as a write strobe signal 4 - 3 reserved - - reserved 2 dma0_chan(2) r/w 0 channel select these three bits select which t/e1 channel within the xrt86vl34 uses the transmit dma_0 (write) interface. 000 = channel 0 001 = channel 1 001 = channel 2 011 = channel 3 1xx = reserved 1 dma0_chan(1) r/w 0 0 dma0_chan(0) r/w 0
xrt86vl34 41 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 21: dma 1 (r ead ) c onfiguration r egister (d1rcr) h ex a ddress : 0 x n119 b it f unction t ype d efault d escription -o peration 7-6 reserved - - reserved 7 dma1 rst r/w 0 dma_1 reset this bit resets the receive dma (read) channel 1 0 = normal operation. 1 = a zero to one transition resets the receive dma (read) channel 1. 6 dma1 enb r/w 0 dma1_enb this bit enables the receive dma_1 (read) interface. after a receive dma is enabled, dma transfers are only requested when the receive cell buffer contains a complete message or cell. the dma read channel is used by the e1 framer to transfer data from the hdlc buffers within the e1 framer to external memory. the dma read cycle starts by e1 framer asserting the dma request ( req1) ?low?, then the external dma controller should drive the dma acknowl - edge ( ack1) ?low? to indicate that it is ready to receive the data. the e1 framer should place new data on the microprocessor data bus each time the read signal is strobed low if the rd is configured as a read strobe. if rd is configured as a direction signal, then the e1 framer would place new data on the microprocessor data bus each time the write signal (wr) is strobed low. 0 = disables the dma_1 (read) interface 1 = enables the dma_1 (read) interface 5 rd type r/w 0 read type select this bit selects the function of the rd signal. 0 = rd functions as a read strobe signal 1 = rd acts as a direction signal (indicates whether the current bus cycle is a read or write operation), and wr works as a data strobe. 4 - 3 reserved - - reserved 2 dma1_chan(2) r/w 0 channel select these three bits select which t/e1 channel within the chip uses the receive dma_1 (read) interface. 000 = channel 0 001 = channel 1 001 = channel 2 011 = channel 3 1xx = reserved 1 dma1_chan(1) r/w 0 0 dma1_chan(0) r/w 0
xrt86vl34 42 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 22: i nterrupt c ontrol r egister (icr) h ex a ddress : 0 x n11a b it f unction t ype d efault d escription -o peration 7-3 reserved - - reserved 2 int_wc_rur r/w 0 interrupt write-to-clear or reset-upon-read select this bit configures all interrupt status bits to be either reset upon read or write-to-clear 0 = configures all interrupt status bits to be reset upon read (rur). 1= configures all interrupt status bits to be write-to-clear (wc). 1 enbclr r/w 0 interrupt enable auto clear this bit configures all interrupt enable bits to clear or not clear after reading the interrupt status bit. 0= configures all interrupt enable bits to not cleared after reading the interrupt status bit. the corresponding interrupt enable bit will stay ?high? after reading the interrupt status bit. 1= configures all interrupt enable bits to clear after reading the interrupt status bit. the corresponding interrupt enable bit will be set to ?low? after reading the interrupt status bit. 0 intrup_enb r/w 0 interrupt enable for framer_n this bit enables the entire e1 framer block for interrupt generation. 0 = disables the e1 framer block for interrupt generation 1 = enables the e1 framer block for interrupt generation
xrt86vl34 43 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 23: lapd s elect r egister (lapdsr) h ex a ddress : 0 x n11b b it f unction t ype d efault d escription -o peration [7:2] reserved - - reserved [1:0] hdlc controller select[1:0] r/w 0 hdlc controller select[1:0]: these bits permit the user to select any of the three (3) hdlc con - trollers that he/she will use within this particular channel, as depicted below. 00 & 11 - selects hdlc controller # 1 01 - selects hdlc controller # 2 10 - selects hdlc controller # 3 t able 24: p erformance r eport c ontrol r egister (prcr) h ex a ddress : 0 x n11d b it f unction t ype d efault d escription -o peration 7 reserved - - for t1 mode only 6 rlos_out_enb r/w 1 rlos output enable: this bit is used to enable or disable the receive los (rlos_n) out - put pins. 0 - disables the rlos output pin. 1 - enables the rlos output pin. 5-0 reserved - - reserved.
xrt86vl34 44 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 25: g apped c lock c ontrol r egister (gccr) h ex a ddress : 0 x n11e b it f unction t ype d efault d escription -o peration 7 froutclk r/w 0 framer output clock reference this bit is used to enable or disable high-speed t1/e1 rate on the t1oscclk and the e1oscclk output pins. by default, the output clock reference on t1oscclk and e1oscclk output pins is 1.544mhz/2.048mhz respectively. by set - ting this bit to a ?1?, the output clock reference on the t1osclk and the e1oscclk is 49.408mhz/65.536mhz for t1/e1 respectively. 0 = disables high-speed rate to be output on the t1oscclk and e1oscclk output pins. standard t1/e1 rate - 1.544mhz/2.048mhz will be output to the t1oscclk and e1oscclk output pins respec - tively. 1 = enables high-speed rate to be output on the t1oscclk and e1oscclk output pins. 6-0 reserved - - reserved
xrt86vl34 45 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 26: t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x n120 b it f unction t ype d efault d escription -o peration 7 txsyncfrd r/w 0 transmit synchronous fraction data interface this bit selects whether txchclk or txserclk will be used for frac - tional data input if the transmit fractional interface is enabled. if txser - clk is selected to clock in fractional data input, txchclk will be used as an enable signal 0 = fractional data is clocked into the chip using txchclk if the trans - mit fractional data interface is enabled. 1 = fractional data is clocked into the chip using txserclk if the trans - mit fractional data interface is enabled. txchclk is used as fractional data enable. n ote : the time slot identifier pins (txchn[4:0]) still indicates the time slot number if the transmit fractional data interface is not enabled. fractional interface can be enabled by setting txfr2048 to 1 6 reserved - - reserved 5 txplclkenb r/w 0 transmit payload clock enable this bit configures the e1 framer to output a regular clock or a payload clock on the transmit serial clock (txserclk) pin when txserclk is configured to be an output. 0 = configures the framer to output a 2.048mhz clock on the txser - clk pin when txserclk is configured as an output. 1 = configures the framer to output a 2.048mhz clock on the txser - clk pin when transmitting payload bits. there will be gaps on the txserclk output pin when transmitting overhead bits. 4 txfr2048 r/w 0 transmit fractional/signaling interface enabled this bit is used to enable or disable the transmit fractional data inter - face, signaling input, as well as the 32mhz transmit clock and the trans - mit overhead signal output. this bit only functions when the device is configured in non-high speed or multiplexed modes of operations. if the device is configured in base rate: 0 = configures the 5 time slot identifier pins (txchn[4:0]) to output the channel number as usual. 1 = configures the 5 time slot identifier pins (txchn[4:0]) into the follow - ing different functions: txchn[0] becomes the transmit serial signaling pin (txsig_n) for sig - naling inputs. signaling data can now be input from the txsig pin if configured appropriately. txchn[1] becomes the transmit fractional data input pin (txfrtd_n) for fractional data input. fractional data can now be input from the txfrtd pin if configured appropriately. txchn[2] becomes the 32 mhz transmit clock output txchn[3] becomes the transmit overhead signal which pulses high on the first bit of each multi-frame. n ote : this bit has no function in the high speed or multiplexed modes of operation. in high-speed or multiplexed modes, txchn[0] functions as txsign for signaling input.
xrt86vl34 46 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 txiclkinv r/w 0 transmit clock inversion (backplane interface) this bit selects whether data transition will happen on the rising or fall - ing edge of the transmit clock. 0 = selects data transition happen on the rising edge of the transmit clocks. 1 = selects data transition happen on the falling edge of the transmit clocks. n ote : this feature is only available for base rate configuration (i.e. non-highspeed, or non-multiplexed modes). 2 txmuxen r/w 0 transmit multiplexed mode enable this bit enables or disables the multiplexed mode on the transmit side. when multiplexed mode is enable, four-channel data from the back- plane interface are multiplexed onto one serial stream and output to the line side. the backplane speed w ill be r unning at 16.384mhz once mul - tiplexed mode is enabled. 0 = disables the multiplexed mode. 1 = enables the multiplexed mode. t able 26: t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x n120 b it f unction t ype d efault d escription -o peration
xrt86vl34 47 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 tximode[1] r/w 0 transmit interface mode selection this bit determines the transmit interface speed. the exact function of these two bits depends on whether multiplexed mode is enabled or dis - abled. table 27 and table 28 shows the functions of these bits for non- multiplexed and multiplexed modes.: 0 tximode[0] r/w 0 t able 26: t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x n120 b it f unction t ype d efault d escription -o peration t able 27: t ransmit i nterface s peed w hen m ultiplexed m od e is d isabled (t x muxen = 0) t x imode[1:0] t ransmit i nterface s peed 00 2.048mbit/s. (base rate) transmit backplane interface signals include: txserclk is an input or output clock at 2.048mhz txmsync is the superframe boundary at 2ms txsync is the single frame boundary at 125 us txser is the base-rate data input 01 2.048mbit/ (high-speed mvip mode) transmit backplane interface signals include: txserclk is an input clock at 2.048mhz txmsync will become the high speed input clock at 2.048mhz to input high-speed data txsync indicates the single frame boundary txser is the high-speed data input 10 4.096mbit/s high-speed mode: transmit backplane interface signals include: txserclk is an input clock at 2.048mhz txmsync will become the high speed input clock at 4.096mhz to input high-speed data txsync indicates the single frame boundary txser is the high-speed data input 11 8.192mbit/s high-speed mode: transmit backplane interface signals include: txserclk is an input clock at 2.048mhz txmsync will become the high speed input clock at 8.192mhz to input high-speed data txsync indicates the single frame boundary txser is the high-speed data input
xrt86vl34 48 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1-0 tximode[1:0] r/w 0 (continued) : transmit backplane interface signals include: txserclk is an input clock at 2.048mhz txmsync will become the high speed input clock at 16.384mhz to input high-speed multiplexed data on the back-plane interface txsync is the single multiplexed frame boundary txser is the high-speed data input n ote : in high speed mode, transmit data is sampled on the rising edge of the 16mhz clock edge. t able 26: t ransmit i nterface c ontrol r egister (ticr) h ex a ddress :0 x n120 b it f unction t ype d efault d escription -o peration t able 28: t ransmit i nterface s peed when m ultiplexed m od e is e nabled (t x muxen = 1) t x imode[1:0] t ransmit i nterface s peed 00 reserved 01 16.384mhz bit multiplexed mode: the transmit interface is taking four-channel multi- plexed data at a rate of 16.384mbit/s from channe l 0 and bit-demultiplexing the serial data into 4 chan - nels and output to the line on channels 0 through 3 . the txsync signal pulses ?high? during the first b it of each e1 frame. 10 hmvip high-speed multiplexed mode enabled: transmit interface is taking four-channel multi- plexed data at a rate of 16.384mbit/s from channe l 0 and byte-demultiplexing the serial data into 4 channels and output to the line on channels 0 through 3. the txsync signal pulses ?high? during the last two bits of the previous e1 frame and the first two bits of the current e1 frame. 11 h.100 high-speed multiplexed mode enabled : transmit interface is taking four-channel multi- plexed data at a rate of 16.384mbit/s from channe l 0 and byte-demultiplexing the serial data into 4 channels and output to the line on channels 0 through 3. the txsync signal pulses ?high? during the last bit of the previous e1 frame and the first b it of the current e1 frame.
xrt86vl34 49 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 29: prbs c ontrol a nd s tatus r egister 0 (prbscsr0) h ex a ddress : 0 xn 121 b it f unction t ype d efault d escription -o peration 3 prbs_switch r/w 0 prbs switch this bit enables or disables the prbs switch function within the xrt86vl34 device. by enabling the prbs switch function, prbs functionality will be switched between the receive and transmit framer. e1 receive framer will generate the prbs pattern and insert it onto the receive backplane interface, and e1 transmit framer will be monitoring the transmit backplane interface for prbs pattern and declare prbs lock if prbs has locked onto the input pattern. if prbs switch is disabled, e1 transmit framer will generate the prbs pattern to the line interface and the receive framer will be monitoring the line for prbs/qrts pattern and declare prbs lock if prbs has locked onto the input pattern. 0 = disables the prbs switch feature. 1 = enables the prbs switch feature. 2 ber[1] r/w 0 bit error rate this bit is used to insert prbs bit error at the rates presented at the table below. the exact function of this bit depends on whether prbs switch function is enabled or not. (bit 3 within this register). if the prbs switch function is disabled, bit error will be inserted by the e1 transmit framer out to the line interface if this bit is enabled. if the prbs switch function is enabled, bit error will be inserted by the e1 receive framer out to the receive backplane interface if this bit is enabled. 1 ber[0] r/w 0 ber[1:0] bit error rate 00 disable bit error insertion to the transmit output or receive backplane interface 01 bit error is inserted to the transmit output or receive backplane interface at a rate of 1/1000 (one out of one thousand) 10 bit error is inserted to the transmit output or receive backplane interface at a rate of 1/ 1,000,000 (one out of one million) 11 disable bit error insertion to the transmit output or receive backplane interface
xrt86vl34 50 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 0 unframedprbs r/w 0 unframed prbs pattern this bit enables or disables unframed prbs/qrts pattern genera - tion (i.e. all timeslots and framing bits are all prbs/qrts data). the exact function of this bit depends on whether prbs switch function is enabled or not. (bit 3 within this register). if prbs switch function is disabled, e1 transmit framer will gener - ate an unframed prbs 15 or qrts pattern to the line side if this bit is enabled. if prbs switch function is enabled, e1 receive framer will gener - ate an unframed prbs 15 or qrts pattern to the receive back - plane interface if this bit is enabled. 0 - enables an unframed prbs/qrts pattern generation to the line interface or to the receive backplane interface 1 - disables an unframed prbs/qrts pattern generation to the line interface or to the receive backplane interface t able 29: prbs c ontrol a nd s tatus r egister 0 (prbscsr0) h ex a ddress : 0 xn 121 b it f unction t ype d efault d escription -o peration
xrt86vl34 51 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 30: r eceive i nterface c ontrol r egister (ricr) h ex a ddress : 0 xn 122 b it f unction t ype d efault d escription -o peration 7 rxsyncfrd r/w 0 receive synchronous fraction data interface this bit selects whether rxchclk or rxserclk will be used for fractional data output if receive fractional interface is enabled. if rxserclk is selected to clock out fractional data, rxchclk will be used as an enable signal 0 = fractional data is clocked out of the chip using rxchclk if the receive fractional interface is enabled. 1 = fractional data is clocked out of the chip using rxserclk if the receive fractional interface is enabled. rxchclk is used as fractional data enable. n ote : the time slot identifier pins (rxchn[4:0]) still indicates the time slot number if the receive fractional data interface is not enabled. fractional interface can be enabled by setting rxfr2048 to 1 6 reserved - - reserved 5 rxplclkenb r/w 0 receive payload clock enable this bit configures the e1 framer to either output a regular clock or a payload clock on the receive serial clock (rxserclk) pin when rxserclk is config - ured to be an output. 0 = configures the framer to output a 2.048mhz clock on the rxserclk pin when rxserclk is configured as an output. 1 = configures the framer to output a 2.048mhz clock on the rxserclk pin when receiving payload bits. there will be gaps on the rxserclk output pin when receiving overhead bits. 4 rxfr2048 r/w 0 receive fractional/signaling interface enabled this bit is used to enable or disable the receive fractional output interface, receive signaling output, the serial channel number output, as well as the 8khz and the received recovered clock output. this bit only functions when the device is configured in non-high speed or multiplexed modes of opera - tions. if the device is configured in base rate: 0 = configure the 5 time slot identifier pins (rxchn[4:0]) to output the channel number in parallel as usual. 1 = configure the 5 time slot identifier pins (rxchn[4:0]) into the following dif - ferent functions: rxchn[0] becomes the receive serial signaling output pin (rxsig_n) for sig - naling outputs. signaling data can now be output to the rxsig pin if config - ured appropriately. rxchn[1] becomes the receive fractional data output pin (rxfrtd_n) for fractional data output. fractional data can now be output to the rxfrtd pin if configured appropriately. rxchn[2] outputs the serial channel number rxchn[3] outputs an 8khz clock signal. rxchn[4] outputs the received recovered clock signal (2.048mhz for e1) n ote : this bit has no function in the high speed or multiplexed modes of operation. in high-speed or multiplexed modes, rxchn[0] outputs the signaling data and rxchn[4] outputs the recovered clock.
xrt86vl34 52 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 rxiclkinv n/a 0 receive clock inversion (backplane interface) this bit selects whether data transition will happen on the rising or fa lling edge of the receive clock. 0 = selects data transition happen on the rising edge of the receive clocks. 1 = selects data transition happen on the falling edge of the receive clocks. n ote : this feature is only available for base rate configuration (i.e. non- highspeed, or non-multiplexed modes). 2 rxmuxen r/w 0 receive multiplexed mode enable this bit enables or disables the multiplexed mode on the receive side. when multiplexed mode is enable, four channels data from the line side are multi - plexed onto one serial stream and output to the back-plane interface on rxser. the backplane speed will become 16.384mhz once multiplexed mode is enabled. 0 = disables the multiplexed mode. 1 = enables the multiplexed mode. t able 30: r eceive i nterface c ontrol r egister (ricr) h ex a ddress : 0 xn 122 b it f unction t ype d efault d escription -o peration
xrt86vl34 53 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 rximode[1] r/w 0 receive interface mode selection this bit determines the receive interface speed. the exact function of these two bits depends on whether receive multiplexed mode is enabled or dis - abled. table 31 and table 32 shows the functions of these two bits for non- multiplexed and multiplexed modes.: 0 rximode[0] r/w 0 t able 30: r eceive i nterface c ontrol r egister (ricr) h ex a ddress : 0 xn 122 b it f unction t ype d efault d escription -o peration t able 31: r eceive i nterface s peed w hen m ultiplexed m ode is d isabled (t x muxen = 0) r x imode[1:0] r eceive i nterface s peed 00 2.048mbit/s. (base rate mode) receive backplane interface signals include: rxserclk is an input or output clock at 2.048mhz rxsync is an input or output signal which indicates the receive singe frame boundary rxser is the base-rate data output 01 2.048mbit/s (high-speed mvip mode) receive backplane interface signals include: rxserclk is an input clock at 2.048mhz rxsync is an input signal which indicates the receive singe frame boundary rxser is the high-speed data output 10 4.096mbit/s high-speed mode: receive backplane interface signals include: rxserclk is an input clock at 4.096mhz rxsync is an input signal which indicates the receive singe frame boundary rxser is the high-speed data output 11 8.192mbit/s high-speed mode: receive backplane interface signals include: rxserclk is an input clock at 8.192mhz rxsync is an input signal which indicates the receive singe frame boundary rxser is the high-speed data output
xrt86vl34 54 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1-0 rximode r/w 0 (continued): receive backplane interface signals include: rxserclk is an input clock at 16.384mhz rxsync is an input signal which indicates the multiplexed frame boundary. the length of rxsync depends on the multiplexed mode selected. rxser is the high-speed data output n ote : in high speed mode, receive data is clocked out on the rising edge of the 16mhz clock edge. t able 30: r eceive i nterface c ontrol r egister (ricr) h ex a ddress : 0 xn 122 b it f unction t ype d efault d escription -o peration t able 32: r eceive i nterface s peed when m ultiplexed m ode is e nabled (t x muxen = 1) t x imode[1:0] t ransmit i nterface s peed 00 reserved 01 16.384mhz bit-multiplexed mode receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing the four- channel data into one 16.384mhz serial stream and out- put to channel 0 of the receive serial output (rxser). the rxsync signal pulses ?high? during the framing bit of each e1 frame. 10 hmvip high-speed multiplexed mode : receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing the four- channel data into one 16.384mhz serial stream and out- put to channel 0 of the receive serial output (rxser). the rxsync signal pulses ?high? during the last two bits of the previous e1 frame and the first two bits of the current e1 frame. 11 h.100 high-speed multiplexed mode : receive interface is taking data from the four liu input channels 0 through 3 and byte-multiplexing the four- channel data into one 16.384mhz serial stream and out- put to channel 0 of the receive serial output (rxser). the rxsync signal pulses ?high? during the last bit of the previous e1 frame and the first bit of the current e1 frame.
xrt86vl34 55 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 33: prbs c ontrol and s tatus r egister 1 (prbscsr1) h ex a ddress : 0 xn 123 b it f unction t ype d efault d escription -o peration 7 prbstyp r/w 0 prbs pattern type this bit selects the type of prbs pattern that the e1 transmit/ receive framer will generate or detect. prbs 15 (x 15 + x 14 +1) polynomial or qrts (quasi-random test signal) pattern can be generated by the transmit or receive framer depending on whether prbs switch function is enabled or not (bit 3 in register 0xn121). if the prbs switch function is disabled, e1 transmit framer will gen - erate either prbs 15 or qrts pattern and output to the line inter - face. prbs 15 or qrts pattern depends on the setting of this bit. if the prbs switch function is enabled, e1 receive framer will gen - erate either prbs 15 or qrts pattern and output to the receive back plane interface. prbs 15 or qrts pattern depends on the setting of this bit. 0 = enables the prbs 15 (x 15 + x 14 +1) polynomial generation. 1 = enables the qrts (quasi-random test signal) pattern genera - tion. 6 errorins r/w 0 error insertion this bit is used to insert a single prbs/qrts error to the transmit or receive output depending on whether prbs switch function is enabled or not. (bit 3 in register 0xn121). if the prbs switch function is disabled, e1 transmit framer will insert a single prbs/qrts error and output to the line interface if this bit is enabled. if the prbs switch function is enabled, e1 receive framer will insert a single prbs/qrts error and output to the receive back plane interface if this bit is enabled. a ?0? to ?1? transition will cause one output bit inverted in the prbs/ qrts stream. this bit only works if prbs generation is enabled. 5 datainv r/w 0 prbs data invert: this bit inverts the transmit prbs/qrts output data and the receive prbs/qrts input data. the exact function of this bit depends on whether prbs switch function is enabled or not. (bit 3 in register 0xn121). if the prbs switch function is disabled and if this bit is enabled, e1 transmit framer will invert the prbs/qrts data before it outputs to the line interface, and the e1 receive framer will invert the incoming prbs/qrts data before it receives it. if the prbs switch function and this bit are both enabled, e1 receive framer will invert the prbs/qrts data before it outputs to the line interface, and the e1 transmit framer w ill invert the incoming prbs/qrts data before it receives it. 0 - transmit and receive framer will not invert the transmit prbs/ qrts and receive prbs data. 1 - transmit and receive framer will invert the transmit prbs/ qrts and receive prbs data.
xrt86vl34 56 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 4 rxprbslock ro 0 lock status this read only bit field indicates whether or not the receive or transmit prbs lock has obtained. the exact function of this bit depends on whether prbs switch function is enabled or not. (bit 3 in register 0xn121). if the prbs switch function is disabled, e1 receive framer will declare lock if prbs/qrts has locked onto the input pattern. if the prbs switch function is disabled, e1 transmit framer will declare lock if prbs/qrts has locked onto the input pattern. 0 = indicates the receive prbs/qrts has not locked onto the input patterns. 1 = indicates the receive prbs/qrts has locked onto the input patterns. 3 rxprbsenb r/w 0 receive prbs detection/generation enable this bit enables or disables the receive prbs/qrts pattern detec - tion or generation. the exact function of this bit depends on whether prbs switch function is enabled or not. (bit 3 in register 0xn121). if the prbs switch function is disabled and if this bit is enabled, e1 receive framer will detect the incoming prbs/qrts pattern from the line side and declare prbs/qrts lock if incoming data locks onto the prbs/qrts pattern. if the prbs switch function and this bit are both enabled, e1 trans - mit framer will detect the incoming prbs/qrts pattern from the transmit backplane interface and declare prbs/qrts lock if incom - ing data locks onto the prbs/qrts pattern. 0 = disables the receive prbs/qrts pattern detection. 1 - enables the receive prbs/qrts pattern detection. 2 txprbsenb r/w 0 transmit prbs generation enable this bit enables or disables the transmit prbs pattern generator. the exact function of this bit depends on whether prbs switch function is enabled or not. (bit 3 in register 0xn121). if prbs switch function is disabled, e1 transmit framer will gener - ate the prbs 15 or qrts pattern to the line side if this bit is enabled. if prbs switch function is enabled, e1 receive framer will gener - ate the prbs 15 or qrts pattern to the receive backplane interface if this bit is enabled. 0 = disables the transmit prbs/qrts pattern generator. 1 - enables the transmit prbs/qrts pattern generator. 1 rxbypass r/w 0 receive framer bypass this bit enables or disables the receive e1 framer bypass. 0 = disables the receive e1 framer bypass. 1 - enables the receive e1 framer bypass 0 txbypass r/w 0 transmit framer bypass this bit enables or disables the transmit e1 framer bypass. 0 = disables the transmit e1 framer bypass. 1 - enables the transmit e1 framer bypass t able 33: prbs c ontrol and s tatus r egister 1 (prbscsr1) h ex a ddress : 0 xn 123 b it f unction t ype d efault d escription -o peration
xrt86vl34 57 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 34: l oopback c ode c ontrol r egister (lccr) h ex a ddress : 0 xn 124 b it f unction t ype d efault d escription -o peration 7-0 reserved - - for t1 mode only t able 35: t ransmit l oopback c oder r egister (tlcr) h ex a ddress : 0 xn 125 b it f unction t ype d efault d escription -o peration 7-0 reserved - - for t1 mode only t able 36: r eceive l oopback a ctivation c ode r egister (rlacr) h ex a ddress : 0 xn 126 b it f unction t ype d efault d escription -o peration 7-0 reserved for t1 mode only t able 37: r eceive l oopback d eactivation c ode r egister (rldcr) h ex a ddress : 0 xn 127 b it f unction t ype d efault d escription -o peration 7-0 reserved for t1 mode only t able 38: d efect d etection e nable r egister (dder) h ex a ddress : 0 xn 129 b it f unction t ype d efault d escription -o peration 7 defdet r/w 1 for defect detection per ansi t1.231-1997 and t1.403-1999, user should leave this bit set to ?1?.
xrt86vl34 58 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 39: t ransmit sa s elect r egister (tsasr) h ex a ddress : 0 xn 130 b it f unction t ype d efault d escription -o peration 7 txsa8sel r/w 0 transmit sa8 bit select this bit determines whether national bit (sa8) is inserted from the transmit serial input (txser_n) pin or from the transmit sa8 regis - ter (register address = 0xn137). 0 = selects sa 8 to be inserted from the transmit serial input (txser_n) input pin. 1 = selects sa 8 to be inserted from the transmit sa8 register (register address = 0xn137) 6 txsa7sel r/w 0 transmit sa7 bit select this bit determines whether national bit (sa7) is inserted from the transmit serial input (txser_n) pin or from the transmit sa7 regis - ter (register address = 0xn136). 0 = selects sa 7 to be inserted from the transmit serial input (txser_n) input pin. 1 = selects sa 7 to be inserted from the transmit sa7 register (register address = 0xn136) 5 txsa6sel r/w 0 transmit sa6 bit select this bit determines whether national bit (sa6) is inserted from the transmit serial input (txser_n) pin or from the transmit sa6 regis - ter (register address = 0xn135). 0 = selects sa 6 to be inserted from the transmit serial input (txser_n) input pin. 1 = selects sa 6 to be inserted from the transmit sa6 register (register address = 0xn135) 4 txsa5sel r/w 0 transmit sa5bit select this bit determines whether national bit (sa5) is inserted from the transmit serial input (txser_n) pin or from the transmit sa5 regis - ter (register address = 0xn134). 0 = selects sa 5 to be inserted from the transmit serial input (txser_n) input pin. 1 = selects sa 5 to be inserted from the transmit sa5 register (register address = 0xn134) 3 txsa4sel r/w 0 transmit sa4 bit select this bit determines whether national bit (sa4) is inserted from the transmit serial input (txser_n) pin or from the transmit sa4 regis - ter (register address = 0xn133). 0 = selects sa 4 to be inserted from the transmit serial input (txser_n) input pin. 1 = selects sa 4 to be inserted from the transmit sa4 register (register address = 0xn133)
xrt86vl34 59 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 lb1enb r/w 0 local loopback 1 auto enable this bit enables or disables local loopback mode when the national bits (sa5, sa6) and the a bit (remote alarm bit) received from the transmit backplane interface follows a specific pattern. local loopback is activated when the national bits (sa5, sa 6) and a bit (remote alarm bit) follow the following pattern from the transmit serial input. (txser_n pin) sa5 = 00000000 occur for 8 consecutive times sa6 = 11111111 occur for 8 consecutive times a = 11111111 occur for 8 consecutive times n ote : this feature only works if sa bits are provided from the transmit serial input pin (txser_n) 1 lb2enb r/w 0 local loopback 2 auto enable this bit enables or disables local loopback mode when the national bits (sa5, sa6) received from the transmit backplane interface fol - lows a specific pattern. local loopback is activated when the national bits (sa5, sa 6) and a bit (remote alarm bit) follow the following pattern from the transmit serial input. (txser_n pin) sa5 = 00000000 occur for 8 consecutive times, and sa6 = 10101010 occur for 8 consecutive times, and a = 11111111 occur for 8 consecutive times n ote : this feature only works if sa bits are provided from the transmit serial input pin (txser_n) 0 lbrenb r/w 0 local loopback release enable this bit releases the local loopback mode when the national bits (sa5, sa6) received from the transmit backplane interface follows a specific pattern. local loopback is released when the national bits (sa5, sa 6) follow the following pattern from the transmit serial input. (txser_n pin) sa5 = 00000000 occur for 8 consecutive times sa6 = 00000000 occur for 8 consecutive times n ote : this feature only works if sa bits are provided from the transmit serial input pin (txser_n) t able 39: t ransmit sa s elect r egister (tsasr) h ex a ddress : 0 xn 130 b it f unction t ype d efault d escription -o peration
xrt86vl34 60 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 40: t ransmit sa a uto c ontrol r egister 1 (tsacr1) h ex a ddress : 0 xn 131 b it f unction t ype d efault d escription -o peration 7 loslfa_1_enb r/w 0 los/lfa 1 automatic transmission this bit enables the automatic sa-bit transmission upon detecting loss of signal (los) or loss of frame alignment (lfa) condition. upon detecting loss of signal or loss of frame alignment condi - tion, e1 framer will transmit the sa5 bit as ?1?, and sa6 bit as ?0? pat - tern. see table 41 for the transmit sa5, sa6, and a bit pattern upon detecting los or lfa conditions. 6 los_1_enb r/w 0 los 1 automatic transmission this bit enables the auto sa-bit transmission upon detecting loss of signal (los) condition. upon detecting loss of signal condition, e1 framer will transmit the alarm bit (a bit) as ?1?, sa5 bit as ?1?, and sa6 bit as ?1110? pattern. see table 41 for the transmit sa5, sa6, and a bit pattern upon detecting los condition. 5 loslfa_2_enb r/w 0 los/lfa 2 automatic transmission this bit enables the auto sa-bit transmission upon detecting loss of signal (los) or loss of frame alignment (lfa) condition. upon detecting loss of signal or loss of frame alignment condi - tion, e1 framer will transmit the alarm bit (a bit) as ?1?, sa5 bit as ?0?, and sa6 bit as ?0? pattern. see table 41 for the transmit sa5, sa6, and a bit pattern upon detecting los or lfa conditions. 4 loslfa_3_enb r/w 0 los/lfa 3 automatic transmission this bit enables the auto sa-bit transmission upon detecting loss of signal (los) or loss of frame alignment (lfa) condition. upon detecting loss of signal or loss of frame alignment condi - tion, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, and sa6 bit as ?1100? pattern. see table 41 for the transmit sa5, sa6, and a bit pattern upon detecting los/lfa conditions. 3 loslfa_4_enb r/w 0 los/lfa 4 automatic transmission this bit enables the auto sa-bit transmission upon detecting loss of signal (los) or loss of frame alignment (lfa) condition. upon detecting loss of signal or loss of frame alignment condi - tion, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, and sa6 bit as ?1110? pattern. see table 41 for the transmit sa5, sa6, and a bit pattern upon detecting los/lfa conditions.
xrt86vl34 61 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 the following table demonstrates the conditions on the receive side which trigger the automatic sa, and a bit transmission when tsacr1 bits are enabled. 2 nop_enb r/w 0 no power automatic transmission this bit enables the auto sa-bit transmission upon detecting loss of power condition. the xrt86vl34 device recognizes the loss of power condition by monitoring the loss of power input pin (pin ab1). when the loss of power input pin is high indicates a loss of power condition is occurring. when the loss of power input pin is low indicates no loss of power condition detected. upon detecting loss of power condition, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, and sa6 bit as ?1000? pattern. see table 41 for the transmit sa5, sa6, and a bit pattern upon detecting loss of power condition. 1 nop_loslfa_enb r/w 0 no power and los/lfa automatic transmission this bit enables the auto sa-bit transmission upon detecting the fol - lowing two conditions: 1. upon loss of power and loss of signal (los) or 2. upon loss of power and loss of frame alignment (lfa) when the e1 framer detects any one of the above two conditions, e1 framer will transmit the alarm bit (a bit) as ?1?, sa5 bit as ?1?, sa6 bit as ?1000? pattern. see table 41 for the transmit sa5, sa6, and a bit format upon detecting loss of power and los/lfa conditions. 0 los_2_enb r/w 0 los 3 automatic transmission this bit enables the auto sa-bit transmission upon detecting loss of signal (los) condition. upon detecting loss of signal condition, e1 framer will transmit the sa5 and sa6 bit as an auxiliary (10101010...) pattern see table 41 for the transmit sa5, sa6, and a bit format upon detecting los condition. t able 41: c onditions on r eceive side w hen tsacr1 bits a re enabled c onditions a ctions - sending pattern c omments a s a 5 s a 6 loslfa_1_enb: loss of signal or loss of frame alignment x 1 0000 los/lfa at te (fc2) los_1_enb: loss of signal 1 1 1110 los (fc3) loslfa_2_enb: los or lfa 1 0 0000 los/lfa (fcl) loslfa_3_enb: los or lfa 0 1 1100 los/lfa (fc4) loslfa_4_enb: los or lfa 0 1 1110 los/lfa (fc3&fc4) nop_enb: loss of power 0 1 1000 loss of power at nt1 nop_loslfa_enb: loss of power and los or lfa 1 1 1000 loss of power and los/lfa los_2_enb: los auxp pattern los (fc1). transmit auxp pattern t able 40: t ransmit sa a uto c ontrol r egister 1 (tsacr1) h ex a ddress : 0 xn 131 b it f unction t ype d efault d escription -o peration
xrt86vl34 62 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 42: t ransmit sa a uto c ontrol r egister 2 (tsacr2) h ex a ddress : 0 xn 132 b it f unction t ype d efault d escription -o peration 7 ais_1_enb r/w 0 ais reception this bit enables the automatic sa-bit transmission upon detecting ais condition. upon detecting the ais condition, e1 framer will transmit the alarm bit (a bit) as ?1?, sa5 bit as ?1?, and sa6 bit as ?1?. see table 43 for the transmit sa5, sa6, and a bit pattern upon detecting ais condition. 6 ais_2_enb r/w 0 ais reception this bit enables the automatic sa-bit transmission upon detecting ais condition. upon detecting the ais condition, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, and sa6 bit as ?1?. see table 43 for the transmit sa5, sa6, and a bit pattern upon detecting ais condition. 5 reserved - - reserved 4 reserved - - reserved 3 crcrep_enb[1] r/w 0 crc report these two bits enable the automatic sa-bit transmission upon detecting far end block error (i.e. received e bit = 0). upon detecting the far end block error (febe) condition, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, sa6 bit as ?0000?, and e bit as ?0? pattern if these two bits are set to ?01?. if these two bits are set to ?10?, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?0?, sa6 bit as ?0000?, and e bit as ?0? pattern upon detecting the far end block error (febe). if these two bits are set to ?11?, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, sa6 bit as ?0001?, and e bit as ?1? pattern upon detecting the far end block error (febe). see table 43 for the transmit sa5, sa6, e, and a bit pattern upon detecting febe condition. 2 crcrep_enb[0] r/w 0 1 crcdet_enb r/w 0 crc detection this bit enables the automatic sa-bit transmission upon detecting crc-4 error condition. upon detecting crc-4 error condition, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, sa6 bit as ?0010?, and e bit as ?1? pattern. see table 43 for the transmit sa5, sa6, e, and a bit pattern upon detecting crc-4 error condition. 0 crcrec and det_enb r/w 0 crc report and detect this bit enables automatic sa-bit transmission upon detecting both far end block error (febe) and crc-4 error conditions. upon detecting both far end block error (febe) and crc-4 error condition, e1 framer will transmit the alarm bit (a bit) as ?0?, sa5 bit as ?1?, sa6 bit as ?0011?, and e bit as ?1? pattern. see table 43 for the transmit sa5, sa6, e, and a bit pattern upon detecting both febe and crc-4 error conditions.
xrt86vl34 63 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 the following table demonstrates the conditions on receive side which trigger the automatic sa, e, and a bits transmission when tsacr2 bits are enabled. t able 43: c onditions on r eceive side w hen tsacr2 bits enabled c onditions a ctions - sending pattern for a s a 5 s a 6 e ais_1_enb 1 1 1111 x ais_2_enb 0 1 1111 x crcrep_enb = 01, crc reported (e = 0) 0 1 0000 0 crcrep_enb = 10, crc reported 0 0 0000 0 crcrep_enb = 11, crc reported 0 1 0001 1 crcdet_enb 0 1 0010 1 crcdet/rep_enb 0 1 0011 1
xrt86vl34 64 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 44: t ransmit sa4 r egister (tsa4r) h ex a ddress : 0 xn 133 b it f unction t ype d efault d escription -o peration 7-0 txsa4[7:0] r/w 11111111 transmit sa4 sequence the content of this register sources the transmit sa4 bits if data link selects sa 4 bit for transmission and if sa4 is inserted from register. (i.e. txsa4enb bit in register 0xn10a = 1 and txsa4sel bit in reg - ister 0xn130 = 1). bit 7 of this register is transmitted in the sa4 position in frame 2 of the crc-4 multiframe, and bit 6 of this register is transmitted in the sa4 position in frame 4 of the crc-4 multiframe,...etc. t able 45: t ransmit sa5 r egister (tsa5r) h ex a ddress : 0 xn 134 b it f unction t ype d efault d escription -o peration 7-0 txsa5[7:0] r/w 11111111 transmit sa5 sequence the content of this register sources the transmit sa5 bits if data link selects sa 5 bit for transmission and if sa5 is inserted from register. (i.e. txsa5enb bit in register 0xn10a = 1 and txsa5sel bit in reg - ister 0xn130 = 1). bit 7 of this register is transmitted in the sa5 position in frame 2 of the crc-4 multiframe, and bit 6 of this register is transmitted in the sa5 position in frame 4 of the crc-4 multiframe,...etc. t able 46: t ransmit sa6 r egister (tsa6r) h ex a ddress : 0 xn 135 b it f unction t ype d efault d escription -o peration 7-0 txsa6[7:0] r/w 11111111 transmit sa6 sequence the content of this register sources the transmit sa6 bits if data link selects sa 6 bit for transmission and if sa6 is inserted from register. (i.e. txsa6enb bit in register 0xn10a = 1 and txsa6sel bit in reg - ister 0xn130 = 1). bit 7 of this register is transmitted in the sa6 position in frame 2 of the crc-4 multiframe, and bit 6 of this register is transmitted in the sa6 position in frame 4 of the crc-4 multiframe,...etc. t able 47: t ransmit sa7 r egister (tsa7r) h ex a ddress : 0 xn 136 b it f unction t ype d efault d escription -o peration 7-0 txsa7[7:0] r/w 11111111 transmit sa7 sequence the content of this register sources the transmit sa7 bits if data link selects sa 7 bit for transmission and if sa7 is inserted from register. (i.e. txsa7enb bit in register 0xn10a = 1 and txsa7sel bit in reg - ister 0xn130 = 1). bit 7 of this register is transmitted in the sa7 position in frame 2 of the crc-4 multiframe, and bit 6 of this register is transmitted in the sa7 position in frame 4 of the crc-4 multiframe,...etc.
xrt86vl34 65 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 48: t ransmit sa8 r egister (tsa8r) h ex a ddress : 0 xn 137 b it f unction t ype d efault d escription -o peration 7-0 txsa8[7:0] r/w 11111111 transmit sa8 sequence the content of this register sources the transmit sa8 bits when data link selects sa 8 bit for transmission and if sa8 is inserted from reg - ister. (i.e. txsa8enb bit in register 0xn10a = 1 and txsa8sel bit in reg - ister 0xn130 = 1). bit 7 of this register is transmitted in the sa8 position in frame 2 of the crc-4 multiframe, and bit 6 of this register is transmitted in the sa8 position in frame 4 of the crc-4 multiframe,...etc.
xrt86vl34 66 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 49: r eceive s a 4 r egister (rsa4r) h ex a ddress : 0 xn 13b b it f unction t ype d efault d escription -o peration 7-0 rxsa4[7:0] ro 00000000 received sa4 sequence the content of this register stores the sa 4 bits in the most recently received crc-4 multiframe. this register is updated when the entire multiframe is received. this register will show the contents of the received sa4 bits if data link selects sa4 bit for reception. (i.e.rxsa4enb bit in register 0xn10ch = 1). bit 7 of this register indicates the received sa4 bit in frame 2 of the crc-4 multiframe, and bit 6 of this register indicates the received sa4 bit in frame 4 of the crc-4 multiframe,...etc. t able 50: r eceive s a 5 r egister (rsa5r) h ex a ddress : 0 xn 13c b it f unction t ype d efault d escription -o peration 7-0 rxsa5[7:0] ro 00000000 received sa5 sequence the content of this register stores the sa 5 bits in the most recently received crc-4 multiframe. this register is updated when the entire multiframe is received. this register will show the contents of the received sa5 bits if data link selects sa5 bit for reception. (i.e.rxsa5enb bit in register 0xn10ch = 1). bit 7 of this register indicates the received sa5 bit in frame 2 of the crc-4 multiframe, and bit 6 of this register indicates the received sa5 bit in frame 4 of the crc-4 multiframe,...etc. t able 51: r eceive s a 6 r egister (rsa6r) h ex a ddress : 0 x n13d b it f unction t ype d efault d escription -o peration 7-0 rxsa6[7:0] ro 00000000 received sa6 sequence the content of this register stores the sa 6 bits in the most recently received crc-4 multiframe. this register is updated when the entire multiframe is received. this register will show the contents of the received sa6 bits if data link selects sa6 bit for reception. (i.e.rxsa6enb bit in register 0xn10ch = 1). bit 7 of this register indicates the received sa6 bit in frame 2 of the crc-4 multiframe, and bit 6 of this register indicates the received sa6 bit in frame 4 of the crc-4 multiframe,...etc.
xrt86vl34 67 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 52: r eceive s a 7 r egister (rsa7r) h ex a ddress : 0 x n13e b it f unction t ype d efault d escription -o peration 7-0 rxsa7[7:0] ro 00000000 received sa7 sequence the content of this register stores the sa 7 bits in the most recently received crc-4 multiframe. this register is updated when the entire multiframe is received. this register will show the contents of the received sa7 bits if data link selects sa7 bit for reception. (i.e.rxsa7enb bit in register 0xn10ch = 1). bit 7 of this register indicates the received sa7 bit in frame 2 of the crc-4 multiframe, and bit 6 of this register indicates the received sa7 bit in frame 4 of the crc-4 multiframe,...etc. t able 53: r eceive s a 8 r egister (rsa8r) h ex a ddress : 0 x n13f b it f unction t ype d efault d escription -o peration 7-0 rxsa8[7:0] ro 00000000 received sa8 sequence the content of this register stores the sa 8 bits in the most recently received crc-4 multiframe. this register is updated when the entire multiframe is received. this register will show the contents of the received sa8 bits if data link selects sa8 bit for reception. (i.e.rxsa8enb bit in register 0xn10ch = 1). bit 7 of this register indicates the received sa8 bit in frame 2 of the crc-4 multiframe, and bit 6 of this register indicates the received sa8 bit in frame 4 of the crc-4 multiframe,...etc.
xrt86vl34 68 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 54: d ata l ink c ontrol r egister (dlcr2) h ex a ddress : 0 x n143 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved. please set this bit to?0? for normal operation. 6 mos abort disable r/w 0 mos abort disable: this bit permits the user to either enable or disable the ?automatic mos abort? feature within transmit hdlc controller # 2. if the user enables this feature, then transmit hdlc controller block # 2 will automatically transmit the abort sequence (e.g., a zero fol - lowed by a string of 7 consecutive ?1s?) whenever it abruptly transi - tions from transmitting a mos type of message, to transmitting a bos type of message. if the user disables this feature, then the transmit hdlc controller block # 2 will not transmit the abort sequence, whenever it abruptly transitions from transmitting a mos-type of message to transmitting a bos-type of message. 0 - enables the ?automatic mos abort? feature 1 - disables the ?automatic mos abort? feature 5 rx_fcs_dis r/w 0 receive frame check sequence (fcs) verification enable/dis - able this bit permits the user to configure the receive hdlc controller block # 2 to compute and verify the fcs value within each incoming lapd message frame. 0 - enables fcs verification 1 - disables fcs verification 4 autorx r/w 0 auto receive lapd message this bit configures the receive hdlc controller block #2 to discard any incoming bos or lapd message frame that exactly match which is currently stored in the receive hdlc2 buffer. 0 = disables this ?auto discard? feature 1 = enables this ?auto discard? feature. 3 tx_abort r/w 0 transmit abort this bit configures the transmit hdlc controller block #2 to trans - mit an abort sequence (string of 7 or more consecutive 1?s) to the remote terminal. 0 - configures the transmit hdlc controller block # 2 to function normally (e.g., not transmit the abort sequence). 1 - configures the transmit hdlc controller block # 2 to transmit the abort sequence.
xrt86vl34 69 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 tx_idle r/w 0 transmit idle (flag sequence byte) this bit configures the transmit hdlc controller block #2 to uncon - ditionally transmit a repeating string of flag sequence octets (0x7e) in the data link channel to the remote terminal. in normal condi - tions, the transmit hdlc controller block will repeatedly transmit the flag sequence octet whenever there is no mos message to transmit to the remote terminal equipment. however, if the user invokes this ?transmit idle sequence? feature, then the transmit hdlc controller block will unconditionally transmit a repeat - ing stream of the flag sequence octet (thereby overwriting all out - bound mos data-link messages). 0 - configures the transmit hdlc controller block # 2 to transmit data-link information in a ?normal? manner. 1 - configures the transmit hdlc controller block # 2 to transmit a repeating string of flag sequence octets (0x7e). n ote : this bit is ignored if the transmit hdlc2 controller is operating in the bos mode - bit 0 (mos/bos) within this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with frame check sequence (fcs) this bit permits the user to configure the transmit hdlc controller block # 2 to compute and append fcs octets to the ?back-end? of each outbound mos data-link message. 0 - configures the transmit hdlc controller block # 2 to not com - pute and append the fcs octets to the back-end of each outbound mos data-link message. 1 - configures the transmit hdlc controller block # 2 to com - pute and append the fcs octets to the back-end of each outbound mos data-link message. n ote : this bit is ignored if the transmit hdlc2 controller has been configured to operate in the bos mode - bit 0 (mos/bos) within this register is set to 0. 0 mos/ bos r/w 0 message oriented signaling/bit oriented signaling send this bit permits the user to enable lapd transmission through hdlc controller block # 2 using either bos (bit-oriented signaling) or mos (message-oriented signaling) frames. 0 - transmit hdlc controller block # 2 bos message send. 1 - transmit hdlc controller block # 2 mos message send. n ote : this is not an enable bit. this bit must be set to "0" each time a bos is to be sent. t able 54: d ata l ink c ontrol r egister (dlcr2) h ex a ddress : 0 x n143 b it f unction t ype d efault d escription -o peration
xrt86vl34 70 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 55: t ransmit d ata l ink b yte c ount r egister (tdlbcr2) h ex a ddress : 0 x n144 b it f unction t ype d efault d escription -o peration 7 txhdlc2 bufavail/ bufsel r/w 0 transmit hdlc2 buffer available/buffer select this bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below. if the user is writing data into this register bit: 0 - configures the transmit hdlc2 controller to read out and trans - mit the data, residing within ?transmit hdlc2 buffer # 0", via the data link channel to the remote terminal equipment. 1 - configures the transmit hdlc2 controller to read out and trans - mit the data, residing within the ?transmit hdlc2 buffer #1?, via the data link channel to the remote terminal equipment. if the user is reading data from this register bit: 0 - indicates that ?transmit hdlc2 buffer # 0" is the next available buffer. in this case, if the user wishes to write in the contents of a new ?outbound? data link message into the transmit hdlc2 mes - sage buffer, he/she should proceed to write this message into ?transmit hdlc2 buffer # 0" - address location: 0xn600. 1 - indicates that ?transmit hdlc2 buffer # 1" is the next available buffer. in this case, if the user wishes to write in the contents of a new ?outbound? data link message into the transmit hdlc2 mes - sage buffer, he/she should proceed to write this message into ?transmit hdlc2 buffer # 1" - address location: 0xn700. n ote : if one of these transmit hdlc2 buffers contain a message which has yet to be completely read-in and processed for transmission by the transmit hdlc2 controller, then this bit will automatically reflect the value corresponding to the next available buffer when it is read. changing this bit to the in- use buffer is not permitted. 6-0 tdlbc[6:0] r/w 0000000 transmit hdlc2 message - byte count the exact function of these bits depends on whether the transmit hdlc 2 controller is configured to transmit mos or bos messages to the remote terminal equipment. in bos mode: these bit fields contain the number of repetitions the bos message must be transmitted before the transmit hdlc2 controller gener - ates the transmit end of transfer (txeot) interrupt and halts trans - mission. if these fields are set to 00000000, then the bos message will be transmitted for an indefinite number of times. in mos mode: these bit fields contain the length, in number of octets, of the mes - sage to be transmitted. the length of mos message specified in these bits include header bytes such as the sapi, tei, control field, however, it does not include the fcs bytes.
xrt86vl34 71 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 56: r eceive d ata l ink b yte c ount r egister (rdlbcr2) h ex a ddress : 0 x n145 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc2 buffer-pointer this bit identifies which receive hdlc2 buffer contains the most recently received hdlc2 message. 0 - indicates that receive hdlc2 buffer # 0 contains the contents of the most recently received hdlc message. 1 - indicates that receive hdlc2 buffer # 1 contains the contents of the most recently received hdlc message. 6-0 rdlbc[6:0] r/w 0000000 receive hdlc message - byte count the exact function of these bits depends on whether the receive hdlc controller block #2 is configured to receive mos or bos messages. in bos mode: these seven bits contain the number of repetitions the bos mes - sage must be received before the receive hdlc2 controller gener - ates the receive end of transfer (rxeot) interrupt. if these bits are set to ?0000000?, the message will be received indefinitely and no receive end of transfer (rxeot) interrupt will be generated. in mos mode: these seven bits contain the size in bytes of the hdlc2 message that has been received and written into the receive hdlc buffer. the length of mos message shown in these bits include header bytes such as the sapi, tei, control field, and the fcs bytes.
xrt86vl34 72 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 57: d ata l ink c ontrol r egister (dlcr3) h ex a ddress : 0 x n153 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved. please set this bit to?0? for normal operation. 6 mos abort disable r/w 0 mos abort disable: this bit permits the user to either enable or disable the ?automatic mos abort? feature within transmit hdlc controller # 3. if the user enables this feature, then transmit hdlc controller block # 3 will automatically transmit the abort sequence (e.g., a zero followed by a string of 7 consecutive ?1s?) whenever it abruptly transitions from transmitting a mos type of mes - sage, to transmitting a bos type of message. if the user disables this feature, then the transmit hdlc controller block # 3 will not transmit the abort sequence, whenever it abruptly transitions from transmitting a mos-type of message to transmitting a bos-type of message. 0 - enables the ?automatic mos abort? feature 1 - disables the ?automatic mos abort? feature 5 rx_fcs_dis r/w 0 receive frame check sequence (fcs) verification enable/disable this bit permits the user to configure the receive hdlc controller block # 3 to compute and verify the fcs value within each incoming lapd message frame. 0 - enables fcs verification 1 - disables fcs verification 4 autorx r/w 0 auto receive lapd message this bit configures the receive hdlc controller block #3 to discard any incoming bos or lapd message frame that exactly match which is currently stored in the receive hdlc1 buffer. 0 = disables this ?auto discard? feature 1 = enables this ?auto discard? feature. 3 tx_abort r/w 0 transmit abort this bit configures the transmit hdlc controller block #3 to transmit an abort sequence (string of 7 or more consecutive 1?s) to the remote termi - nal. 0 - configures the transmit hdlc controller block # 3 to function normally (e.g., not transmit the abort sequence). 1 - configures the transmit hdlc controller block # 3 to transmit the abort sequence.
xrt86vl34 73 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 tx_idle r/w 0 transmit idle (flag sequence byte) this bit configures the transmit hdlc controller block #3 to unconditionally transmit a repeating string of flag sequence octets (0x7e) in the data link channel to the remote terminal. in normal conditions, the transmit hdlc controller block will repeatedly transmit the flag sequence octet whenever there is no mos message to transmit to the remote terminal equipment. however, if the user invokes this ?transmit idle sequence? feature, then the transmit hdlc controller block will unconditionally transmit a repeat - ing stream of the flag sequence octet (thereby overwriting all outbound mos data-link messages). 0 - configures the transmit hdlc controller block # 3 to transmit data-link information in a ?normal? manner. 1 - configures the transmit hdlc controller block # 3 to transmit a repeat - ing string of flag sequence octets (0x7e). n ote : this bit is ignored if the transmit hdlc3 controller is operating in the bos mode - bit 0 (mos/bos) within this register is set to 0. 1 tx_fcs_en r/w 0 transmit lapd message with frame check sequence (fcs) this bit permits the user to configure the transmit hdlc controller block # 3 to compute and append fcs octets to the ?back-end? of each outbound mos data-link message. 0 - configures the transmit hdlc controller block # 3 to not compute and append the fcs octets to the back-end of each outbound mos data-link message. 1 - configures the transmit hdlc controller block # 3 to compute and append the fcs octets to the back-end of each outbound mos data-link message. n ote : this bit is ignored if the transmit hdlc3 controller has been configured to operate in the bos mode - bit 0 (mos/bos) within this register is set to 0. 0 mos/ bos r/w 0 message oriented signaling/bit oriented signaling send this bit permits the user to enable lapd transmission through hdlc con - troller block # 3 using either bos (bit-oriented signaling) or mos (mes - sage-oriented signaling) frames. 0 - transmit hdlc controller block # 3 bos message send. 1 - transmit hdlc controller block # 3 mos message send. n ote : this is not an enable bit. this bit must be set to "0" each time a bos is to be sent. t able 57: d ata l ink c ontrol r egister (dlcr3) h ex a ddress : 0 x n153 b it f unction t ype d efault d escription -o peration
xrt86vl34 74 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 58: t ransmit d ata l ink b yte c ount r egister (tdlbcr3) h ex a ddress : 0 x n154 b it f unction t ype d efault d escription -o peration 7 txhdlc3 bufavail/ bufsel r/w 0 transmit hdlc3 buffer available/buffer select this bit has different functions, depending upon whether the user is writing to or reading from this register, as depicted below. if the user is writing data into this register bit: 0 - configures the transmit hdlc3 controller to read out and trans - mit the data, residing within ?transmit hdlc3 buffer # 0", via the data link channel to the remote terminal equipment. 1 - configures the transmit hdlc3 controller to read out and trans - mit the data, residing within the ?transmit hdlc3 buffer #1?, via the data link channel to the remote terminal equipment. if the user is reading data from this register bit: 0 - indicates that ?transmit hdlc3 buffer # 0" is the next available buffer. in this case, if the user wishes to write in the contents of a new ?outbound? data link message into the transmit hdlc3 mes - sage buffer, he/she should proceed to write this message into ?transmit hdlc3 buffer # 0" - address location: 0xn600. 1 - indicates that ?transmit hdlc3 buffer # 1" is the next available buffer. in this case, if the user wishes to write in the contents of a new ?outbound? data link message into the transmit hdlc3 mes - sage buffer, he/she should proceed to write this message into ?transmit hdlc3 buffer # 1" - address location: 0xn700. n ote : if one of these transmit hdlc3 buffers contain a message which has yet to be completely read-in and processed for transmission by the transmit hdlc3 controller, then this bit will automatically reflect the value corresponding to the next available buffer when it is read. changing this bit to the in- use buffer is not permitted. 6-0 tdlbc[6:0] r/w 0000000 transmit hdlc3 message - byte count the exact function of these bits depends on whether the transmit hdlc 3 controller is configured to transmit mos or bos messages to the remote terminal equipment. in bos mode: these bit fields contain the number of repetitions the bos message must be transmitted before the transmit hdlc3 controller gener - ates the transmit end of transfer (txeot) interrupt and halts trans - mission. if these fields are set to 00000000, then the bos message will be transmitted for an indefinite number of times. in mos mode: these bit fields contain the length, in number of octets, of the mes - sage to be transmitted. the length of mos message specified in these bits include header bytes such as the sapi, tei, control field, however, it does not include the fcs bytes.
xrt86vl34 75 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 59: r eceive d ata l ink b yte c ount r egister (rdlbcr3) h ex a ddress : 0 x n155 b it f unction t ype d efault d escription -o peration 7 rbufptr r/w 0 receive hdlc3 buffer-pointer this bit identifies which receive hdlc3 buffer contains the most recently received hdlc1 message. 0 - indicates that receive hdlc3 buffer # 0 contains the contents of the most recently received hdlc message. 1 - indicates that receive hdlc3 buffer # 1 contains the contents of the most recently received hdlc message. 6-0 rdlbc[6:0] r/w 0000000 receive hdlc message - byte count the exact function of these bits depends on whether the receive hdlc controller block #3 is configured to receive mos or bos messages. in bos mode: these seven bits contain the number of repetitions the bos mes - sage must be received before the receive hdlc3 controller gener - ates the receive end of transfer (rxeot) interrupt. if these bits are set to ?0000000?, the message will be received indefinitely and no receive end of transfer (rxeot) interrupt will be generated. in mos mode: these seven bits contain the size in bytes of the hdlc3 message that has been received and written into the receive hdlc buffer. the length of mos message shown in these bits include header bytes such as the sapi, tei, control field, and the fcs bytes.
xrt86vl34 76 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 60: d evice id r egister (devid) h ex a ddress : 0 xn 1fe b it f unction t ype d efault d escription -o peration 7-0 devid[7:0] ro 0x3a devid this register is used to identify the xrt86vl34 framer/liu. the value of this register is 0x3ah. t able 61: r evision id r egister (revid) h ex a ddress : 0 xn 1ff b it f unction t ype d efault d escription -o peration 7-0 revid[7:0] ro 00000001 revid this register is used to identify the revision number of the xrt86vl34. the value of this register for the first revision is a - 0x01h. n ote : the content of this register is subject to change when a newer revision of the device is issued.
xrt86vl34 77 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 62: t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0xn300 to 0 x n31f b it f unction t ype d efault d escription -o peration 7 lapdcntl[1] r/w 1 transmit lapd control these bits select which one of the three transmit lapd controller is config - ured to use d/e time slot (octets 0-31) for transmitting lapd messages. the following table presents the different settings of these two bits . n ote : all three transmit lapd controllers can use d/e timeslots for transmission. however, only transmit lapd controller 1 can use datalink for transmission. register 0xn300 represents d/e time slot 0, and 0xn31f represents d/e time slot 31. 6 lapdcntl[0] 0 5-4 reserved - - reserved (for t1 mode only) lapdcntl[1:0] lapd c ontroller s elected 00 transmit lapd controller 1 01 transmit lapd controller 2 10 the txde[1:0] bits in the transmit signaling and data link select register (tsdlsr - register address - 0xn10a, bit 3-2) determine the data source for d/e time slots. 11 transmit lapd controller 3
xrt86vl34 78 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3-0 txcond(3:0) r/w 0000 transmit channel conditioning for timeslot 0 to 31 these bits allow the user to substitute the input pcm data (octets 0-31) with internally generated conditioning codes prior to transmission to the remote terminal equipment on a per-channel basis. the table below presents the different conditioning codes based on the setting of these bits. n ote : register address 0xn300 represents time slot 0, and address 0xn31f represents time slot 31. t able 62: t ransmit c hannel c ontrol r egister 0-31 (tccr 0-31) h ex a ddress : 0xn300 to 0 x n31f b it f unction t ype d efault d escription -o peration t x c ond [1:0] c onditioning c odes 0x0 / 0xe contents of timeslot octet are unchanged. 0x1 all 8 bits of the selected timeslot octet are inverted (1?s complement) output = (time_slot_octet) xor 0xff 0x2 even bits of the selected timeslot octet are inverted output = (time_slot_octet) xor 0xaa 0x3 odd bits of the selected time slot octet are inverted output = (time_slot_octet) xor 0x55 0x4 contents of the selected timeslot octet will be substituted with the 8 -bit value in the transmit programmable user code register (0xn320-0xn337), 0x5 contents of the timeslot octet will be substituted with the value 0x7f (busy code) 0x6 contents of the timeslot octet will be substituted with the value 0xff (vacant code) 0x7 contents of the timeslot octet will be substituted with the busy time slot code (111#_####), where ##### is the timeslot number 0x8 contents of the timeslot octet will be substituted with the moof code (0x1a) 0x9 contents of the timeslot octet will be substituted with the a-law digital milliwatt pattern 0xa contents of the timeslot octet will be substituted with the -law digital milliwatt pattern 0xb the msb (bit 1) of input data is inverted 0xc all input data except msb is inverted 0xd contents of the timeslot octet will be substituted with the prbs x 15 + x 14 + 1/qrts pattern n ote : prbs x 15 + x 14 + 1 or qrts pattern depends on prbstype selected in the register 0xn123 - bit 7 0xf d/e time slot - the txsigdl[2:0] bits in the transmit sig- naling and data link select register (0xn10a) will deter- mine the data source for d/e time slots.
xrt86vl34 79 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 63: t ransmit u ser c ode r egister 0 - 31 (tucr 0-31) h ex a ddress : 0 x n320 to 0 x n33f b it f unction t ype d efault d escription -o peration 7-0 tucr[7:0] r/w b00010111 transmit programmable user code. these eight bits allow users to program any code in this register to replace the input pcm data when the transmit channel control register (tccr) is configured to replace timeslot octet with pro - grammable user code. (i.e. if tccr is set to ?0x4?) the default value of this register is an idle code (b00010111).
xrt86vl34 80 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 64: t ransmit s ignaling c ontrol r egister 0-31 (tscr 0-31) h ex a ddress : 0 x n340 to 0 xn 35f b it f unction t ype d efault d escription -o peration 7 a (x) r/w see note transmit signaling bit a or x bit this bit allows users to provide signaling bit a for octets 0-31 if channel associated signaling (cas) is enabled and if signaling data is inserted from tscr register (txsigsrc[1:0] = 01 in this register) n ote : users must write to tscr0 (address 0xn340) the correct cas alignment bits (0 bits) in order to get cas sync at the remote terminal. the xyxx bits can be programmed by writing to tscr16 (0xn350) and programming the txsigsrc[1:0] bits within this register to ?b11?. 6 b (y) r/w see note transmit signaling bit b or y bit this bit allows users to provide signaling bit b for octets 0-31 if channel associated signaling (cas) is enabled and if signaling data is inserted from tscr register (txsigsrc[1:0] = 01 in this register) n ote : users must write to tscr0 (address 0xn340) the correct cas alignment bits (0 bits) in order to get cas sync at the remote terminal. the xyxx bits can be programmed by writing to tscr16 (0xn350) and programming the txsigsrc[1:0] bits within this register to ?b11?. 5 c (x) r/w see note transmit signaling bit c or x bit this bit allows users to provide signaling bit c for octets 0-31 if channel associated signaling (cas) is enabled and if signaling data is inserted from tscr register (txsigsrc[1:0] = 01 in this register) n ote : users must write to tscr0 (address 0xn340) the correct cas alignment bits (0 bits) in order to get cas sync at the remote terminal. the xyxx bits can be programmed by writing to tscr16 (0xn350) and programming the txsigsrc[1:0] bits within this register to ?b11?. 4 d (x) r/w see note transmit signaling bit d or x bit this bit allows users to provide signaling bit d in for octets 0-31 if channel associated signaling (cas) is enabled and if signaling data is inserted from tscr register (txsigsrc[1:0] = 01 in this register) n ote : users must write to tscr0 (address 0xn340) the correct cas alignment bits (0 bits) in order to get cas sync at the remote terminal. the xyxx bits can be programmed by writing to tscr16 (0xn350) and programming the txsigsrc[1:0] bits within this register to ?b11?. 3 reserved - see note reserved 2 reserved - see note reserved
xrt86vl34 81 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 n ote : the default value for register address 0xn340 = 0x01, 0xn341-0xn34f = 0xd0, 0xn350 = 0xb3, 0xn351-0xn35f = 0xd0 1 txsigsrc[1] r/w see note channel signaling control these bits determine the source for signaling information. the table below presents the different sources for signaling information corre - sponding to different settings of these two bits . 0 txsigsrc[0] r/w see note t able 64: t ransmit s ignaling c ontrol r egister 0-31 (tscr 0-31) h ex a ddress : 0 x n340 to 0 xn 35f b it f unction t ype d efault d escription -o peration t x sigsrc[1:0] s ignaling source selected 00 signaling data is inserted from input pcm data (txsern pin) 01 signaling data is inserted from this register (tscrs). 10 signaling data is inserted from the transmit overhead input pin (txoh_n) if xrt86vl34 is configured in the base rate configuration and if the transmit signaling interface bit is disabled. (i.e. txmuxen bit = 0, txi- mode[1:0] = 00, and txfr2048 bit = 0 in the transmit interface control register (ticr) register 0xn120). if the transmit signaling interface bit is enabled (i.e. txfr2048 bit = 1 in the trans- mit interface control register (ticr) regis- ter 0xn120), signaling data will be inserted from the transmit signaling input pin (txsig_n) 11 no signaling data is inserted into the input pcm data. setting these two bits to ?11? will configure the xyxx bits only, where x bits are inserted from this register (tscr) and y bit reflects the alarm condition.
xrt86vl34 82 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description
xrt86vl34 83 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 65: r eceive c hannel c ontrol r egister x (rccr 0-31) h ex a ddress : 0 x n360 to 0 xn 37f b it f unction t ype d efault d escription -o peration 7 lapdcntl[1] r/w 1 receive lapd control these bits select which one of the three receive lapd controller w ill be con - figured to use d/e time slot (octets 0-23) for receiving lapd messages . n ote : all three lapd controller can use d/e timeslots for receiving lapd messages. however, only lapd controller 1 can use datalink for reception. n ote : register 0xn360 represents d/e time slot 0, and 0xn37f represents d/e time slot 31. 6 lapdcntl[0] r/w 0 5-4 reserved - - reserved lapdcntl[1:0] r eceive lapd c ontroller s elected 00 receive lapd controller 1 01 receive lapd controller 2 10 the rxsigdl[1:0] bits in the receive sig- naling and data link select register (rsdlsr - address - 0xn10c) determine the data source for receive d/e time slots. 11 receive lapd controller 3
xrt86vl34 84 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3-0 rxcond[3:0] r/w 0000 receive channel conditioning for timeslot 0 to 31 these bits allow the user to substitute the input line data (octets 0-31) with internally generated conditioning codes prior to transmission to the back - plane interface on a per-channel basis. the table below presents the differ - ent conditioning codes based on the setting of these bits. n ote : register address 0xn300 represents time slot 0, and address 0xn31f represents time slot 31. t able 65: r eceive c hannel c ontrol r egister x (rccr 0-31) h ex a ddress : 0 x n360 to 0 xn 37f b it f unction t ype d efault d escription -o peration r x c ond [1:0] c onditioning c odes 0x0 / 0xe contents of timeslot octet are unchanged. 0x1 all 8 bits of the selected timeslot octet are inverted (1?s complement) output = (time_slot_octet) xor 0xff 0x2 even bits of the selected timeslot octet are inverted output = (time_slot_octet) xor 0xaa 0x3 odd bits of the selected time slot octet are inverted output = (time_slot_octet) xor 0x55 0x4 contents of the selected timeslot octet will be substituted with the 8 -bit value in the receive programmable user code register (0xn380-0xn397), 0x5 contents of the timeslot octet will be substituted with the value 0x7f (busy code) 0x6 contents of the timeslot octet will be substituted with the value 0xff (vacant code) 0x7 contents of the timeslot octet will be substituted with the busy time slot code (111#_####), where ##### is the timeslot number 0x8 contents of the timeslot octet will be substituted with the moof code (0x1a) 0x9 contents of the timeslot octet will be substituted with the a-law digital milliwatt pattern 0xa contents of the timeslot octet will be substituted with the -law digital milliwatt pattern 0xb the msb (bit 1) of input data is inverted 0xc all input data except msb is inverted 0xd contents of the timeslot octet will be substituted with the prbs x 15 + x 14 + 1/qrts pattern n ote : prbs x 15 + x 14 + 1 or qrts pattern depends on prbstype selected in the register 0xn123 - bit 7 0xf d/e time slot - the rxsigdl[2:0] bits in the transmit sig- naling and data link select register (0xn10c) will deter- mine the data source for receive d/e time slots.
xrt86vl34 85 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 66: r eceive u ser c ode r egister 0-31 (rucr 0-31) h ex a ddress : 0 x n380 to 0 xn 39f b it f unction t ype d efault d escription -o peration 7-0 rxuser[7:0] r/w 11111111 receive programmable user code. these eight bits allow users to program any code in this register to replace the received data when the receive channel control regis - ter (rccr) is configured to replace timeslot octet with the receive programmable user code. (i.e. if rccr is set to ?0x4?)
xrt86vl34 86 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 67: r eceive s ignaling c ontrol r egister 0-31 (rscr 0-31) h ex a ddress : 0 x n3a0 to 0 xn 3bf b it f unction t ype d efault d escription -o peration 6 sigc_enb r/w 0 signaling substitution enable this bit enables or disables signaling substitution on the receive side on a per channel basis. once signaling substitution is enabled, received signaling bits abcd will be substituted with the abcd val - ues in the receive substitution signaling register (rssr). signaling substitution only occurs in the output pcm data (rxsern). receive signaling array register (rsar - address 0xn500-0xn51f) and the external signaling bus (rxsig_n) output pin will not be affected. 0 = disables signaling substitution on the receive side. 1 = enables signaling substitution on the receive side. 5 oh_enb r/w 0 signaling oh interface output enable this bit enables or disables signaling information to output via the receive overhead pin (rxoh_n) on a per channel basis. the sig - naling information in the receive signaling array registers (rsar - address 0xn500-0xn51f) is output to the receive overhead output pin (rxoh_n) if this bit is enabled. 0 = disables signaling information to output via rxoh_n. 1 = enables signaling information to output via rxoh_n. 4 deb_enb r/w 0 per-channel debounce enable this bit enables or disables the signaling debounce feature on a per channel basis. when this feature is enabled, the per-channel signaling state must be in the same state for 2 superframes before the receive framer updates signaling information on the receive signaling array regis - ter (rsar) and the signaling pin (rxsign). if the signaling bits for two consecutive superframes are not the same, the current state of rsar and rxsig will not change. when this feature is disabled, rsar and rxsig w ill be updated as soon as the receive signaling bits have changed. 0 = disables the signaling debounce feature. 1 = enables the signaling debounce feature.
xrt86vl34 87 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 3 rxsigc[1] r/w 0 signaling conditioning these bits allow user to select the format of signaling substitution on a per-channel basis, as presented in the table below . 2 rxsigc[0] r/w 0 1 rxsige[1] r/w 0 receive signaling extraction. these bits control per-channel signaling extraction as presented in the table below. signaling information can be extracted to the receive signaling array register (rsar), the receive signaling output pin (rxsig_n) if the receive signaling interface is enable, or the receive overhead interface output (rxoh_n) if oh_enb bit is enabled. (bit 5 of this register). 0 rxsige[0] r/w 0 t able 67: r eceive s ignaling c ontrol r egister 0-31 (rscr 0-31) h ex a ddress : 0 x n3a0 to 0 xn 3bf b it f unction t ype d efault d escription -o peration r x sigc[1:0] s ignaling s ubstitution s chemes 00 substitutes all signaling bits with one. 01 enables 16-code (a,b,c,d) signaling substi- tution. users must write to bits 3-0 in the receive sig- naling substitution register (rssr) to provide the 16-code (a,b,c,d) signaling substitution val- ues. 10 enables 4-code (a,b) signaling substitution. users must write to bits 4-5 in the receive sig- naling substitution register (rssr) to provide the 4-code (a,b) signaling substitution values. 11 enables 2-code (a) signaling substitution. users must write to bit 6 in the receive signal- ing substitution register (rssr) to provide the 2-code (a) signaling substitution values. r x sige[1:0] s ignaling e xtraction s chemes 00 no signaling information is extracted. 01 enables 16-code (a,b,c,d) signaling extraction. all signaling bits a,b,c,d will be extracted. 10 enables 4-code (a,b) signaling extraction only signaling bits a,b will be extracted. 11 enables 2-code (a) signaling extraction only signaling bit a will be extracted.
xrt86vl34 88 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 68: r eceive s ubstitution s ignaling r egister 0-31 (rssr 0-31) h ex a ddress 0 x n3c0 to 0 xn 3df b it f unction t ype d efault d escription -o peration 6 sig2-a r/w 0 2-code signaling a this bit provides the value of signaling bit a to substitute the receive signaling bit a on a per channel basis when 2-code signaling substi - tution is enabled. register address 0xn3c0 represents time slot 0, and 0xn3df represents time slot 31. 5 sig4-b r/w 0 4-code signaling b this bit provides the value of signaling bit b to substitute the receive signaling bit b when 4-code signaling substitution is enabled. regis - ter address 0xn3c0 represents time slot 0, and 0xn3df represents time slot 31. 4 sig4-a r/w 0 4-code signaling a this bit provides the value of signaling bit a to substitute the receive signaling bit a when 4-code signaling substitution is enabled. regis - ter address 0xn3c0 represents time slot 0, and 0xn3df represents time slot 31. 3 sig16-d r/w 0 16-code signaling d this bit provides the value of signaling bit d to substitute the receive signaling bit d when 16-code signaling substitution is enabled. reg - ister address 0xn3c0 represents time slot 0, and 0xn3df repre - sents time slot 31. 2 sig16-c r/w 0 16-code signaling c this bit provides the value of signaling bit c to substitute the receive signaling bit c when 16-code signaling substitution is enabled. reg - ister address 0xn3c0 represents time slot 0, and 0xn3df repre - sents time slot 31. 1 sig16-b r/w 0 16-code signaling b this bit provides the value of signaling bit b to substitute the receive signaling bit b when 16-code signaling substitution is enabled. reg - ister address 0xn3c0 represents time slot 0, and 0xn3df repre - sents time slot 31. 0 sig16-a r/w 0 16-code signaling a this bit provides the value of signaling bit a to substitute the receive signaling bit a when 16-code signaling substitution is enabled. reg - ister address 0xn3c0 represents time slot 0, and 0xn3df repre - sents time slot 31.
xrt86vl34 89 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 69: r eceive s ignaling a rray r egister 0 - 31 (rsar 0-31) h ex a ddress : 0xn500 to 0 x n51f b it f unction t ype d efault d escription -o peration 7-4 reserved - - reserved 3 a ro 0 these read only registers reflect the most recently received sig - naling value (a,b,c,d) associated with timeslot 0 to 31. if signaling debounce feature is enabled, the received signaling state must be the same for 2 superframes before this register is updated. if the signaling bits for two consecutive superframes are not the same, the current value of this register will not be changed. if the signaling debounce or sig feature is disabled, this register is updated as soon as the received signaling bits have changed. n ote : the content of this register only has meaning when the framer is using channel associated signaling. 2 b ro 0 1 c ro 0 0 d ro 0
xrt86vl34 90 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 70: lapd b uffer 0 c ontrol r egister (lapdbcr0) h ex a ddress : 0 x n600 b it f unction t ype d efault d escription -o peration 7-0 lapd buffer 0 r/w 0 lapd buffer 0 (96-bytes) auto incrementing this register is used to transmit and receive lapd messages within buffer 0 of the hdlc controller. any one of the hdlc controller can be is chosen in the lapd select register (0xn11b). users should determine the next available buffer by reading the bufaval bit (bit 7 of the transmit data link byte count register 1 (address 0xn114), register 2 (0xn144) and register 3 (0xn154) depending on which hdlc controller is selected. if buffer 0 is available, writing to buffer 0 will insert the message into the outgoing lapd frame after the lapd message is sent and the data from the transmit buffer cannot be retrieved. after detecting the receive end of transfer interrupt (rxeot), users should read the rbufptr bit (bit 7 of the receive data link byte count register 1 (address 0xn115), register 2 (0xn145), or regis - ter 3 (0xn155) depending on which hdlc controller is selected) to determine which buffer contains the received lapd message ready to be read. if rbufptr bit indicates that buffer 0 is available to be read, reading buffer 0 (register 0xn600) continuously will retrieve the entire received lapd message. n ote : when writing to or reading from buffer 0, the register is automatically incremented such that the entire 96 byte lapd message can be written into or read from buffer 0 (register 0xn600) continuously. t able 71: lapd b uffer 1 c ontrol r egister (lapdbcr1) h ex a ddress : 0 x n700 b it f unction t ype d efault d escription -o peration 7-0 lapd buffer 1 r/w 0 lapd buffer 1 (96-bytes) auto incrementing this register is used to transmit and receive lapd messages within buffer 1 of the hdlc controller. any one of the hdlc controller can be is chosen in the lapd select register (0xn11b). users should determine the next available buffer by reading the bufaval bit (bit 7 of the transmit data link byte count register 1 (address 0xn114), register 2 (0xn144) and register 3 (0xn154) depending on which hdlc controller is selected. if buffer 1 is available, writing to buffer 1 will insert the message into the outgoing lapd frame after the lapd message is sent and the data from the transmit buffer 1 can - not be retrieved. after detecting the receive end of transfer interrupt (rxeot), users should read the rbufptr bit (bit 7 of the receive data link byte count register 1 (address 0xn115), register 2 (0xn145), or regis - ter 3 (0xn155) depending on which hdlc controller is selected) to determine which buffer contains the received lapd message ready to be read. if rbufptr bit indicates that buffer 1 is available to be read, reading buffer 1 (register 0xn700) continuously will retrieve the entire received lapd message. n ote : when writing to or reading from buffer 0, the register is automatically incremented such that the entire 96 byte lapd message can be written into or read from buffer 0 (register 0xn600) continuously.
xrt86vl34 91 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 72: pmon r eceive l ine c ode v iolation c ounter msb (rlcvcu) h ex a ddress : 0 x n900 b it f unction t ype d efault d escription -o peration 7 rlcvc[15] rur 0 performance monitor ?receive line code violation? 16-bit counter - upper byte: these reset-upon-read bits, along with that within the pmon receive line code violation counter register lsb combine to reflect the cumulative number of instances that line code violation has been detected by the receive e1 framer block since the last read of this register. this register contains the most significant byte of this 16-bit of the line code violation counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rlcvc[14] rur 0 5 rlcvc[13] rur 0 4 rlcvc[12] rur 0 3 rlcvc[11] rur 0 2 rlcvc[10] rur 0 1 rlcvc[9] rur 0 0 rlcvc[8] rur 0 t able 73: pmon r eceive l ine c ode v iolation c ounter lsb (rlcvcl) h ex a ddress : 0 x n901 b it f unction t ype d efault d escription -o peration 7 rlcvc[7] rur 0 performance monitor ?receive line code violation? 16-bit counter - lower byte: these reset-upon-read bits, along with that within the pmon receive line code violation counter register msb combine to reflect the cumulative number of instances that line code violation has been detected by the receive e1 framer block since the last read of this register. this register contains the least significant byte of this 16-bit of the line code violation counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rlcvc[6] rur 0 5 rlcvc[5] rur 0 4 rlcvc[4] rur 0 3 rlcvc[3] rur 0 2 rlcvc[2] rur 0 1 rlcvc[1] rur 0 0 rlcvc[0] rur 0
xrt86vl34 92 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description . . t able 74: pmon r eceive f raming a lignment b it e rror c ounter msb (rfaecu) h ex a ddress : 0 x n902 b it f unction t ype d efault d escription -o peration 7 rfaec[15] rur 0 performance monitor ?receive framing alignment error 16-bit counter? - upper byte: these reset-upon-read bits, along with that within the ?pmon receive framing alignment error counter register lsb? combine to reflect the cumulative number of instances that the receive framing alignment errors has been detected by the receive e1 framer block since the last read of this register. this register contains the most significant byte of this 16-bit of the receive framing alignment error counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rfaec[14] rur 0 5 rfaec[13] rur 0 4 rfaec[12] rur 0 3 rfaec[11] rur 0 2 rfaec[10] rur 0 1 rfaec[9] rur 0 0 rfaec[8] rur 0 t able 75: pmon r eceive f raming a lignment b it e rror c ounter lsb (rfaecl) h ex a ddress : 0 x n903 b it f unction t ype d efault d escription -o peration 7 rfaec[7] rur 0 performance monitor ?receive framing alignment error 16-bit counter? - lower byte: these reset-upon-read bits, along with that within the ?pmon receive framing alignment error counter register msb? combine to reflect the cumulative number of instances that the receive framing alignment errors has been detected by the receive e1 framer block since the last read of this register. this register contains the least significant byte of this 16-bit of the receive framing alignment error counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rfaec[6] rur 0 5 rfaec[5] rur 0 4 rfaec[4] rur 0 3 rfaec[3] rur 0 2 rfaec[2] rur 0 1 rfaec[1] rur 0 0 rfaec[0] rur 0
xrt86vl34 93 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 76: pmon r eceive s everely e rrored f rame c ounter (rsefc) h ex a ddress : 0 x n904 b it f unction t ype d efault d escription -o peration 7 rsefc[7] rur 0 performance monitor - receive severely errored frame counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that receive severely errored frames have been detected by the e1 framer since the last read of this register. severely errored frame is defined as the occurrence of two consec - utive errored frame alignment signals without causing loss of frame condition. 6 rsefc[6] rur 0 5 rsefc[5] rur 0 4 rsefc[4] rur 0 3 rsefc[3] rur 0 2 rsefc[2] rur 0 1 rsefc[1] rur 0 0 rsefc[0] rur 0 t able 77: pmon r eceive crc-4 b it e rror c ounter - msb (rsbbecu) h ex a ddress : 0 x n905 b it f unction t ype d efault d escription -o peration 7 rsbbec[15] rur 0 performance monitor ?receive synchronization bit error 16-bit counter? - upper byte: these reset-upon-read bits, along with that within the ?pmon receive synchronization bit error counter register lsb? combine to reflect the cumulative number of instances that the receive syn - chronization bit errors has been detected by the receive e1 framer block since the last read of this register. this register contains the most significant byte of this 16-bit of the receive synchronization bit error counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rsbbec[14] rur 0 5 rsbbec[13] rur 0 4 rsbbec[12] rur 0 3 rsbbec[11] rur 0 2 rsbbec[10] rur 0 1 rsbbec[9] rur 0 0 rsbbec[8] rur 0 t able 78: pmon r eceive crc-4 b lock e rror c ounter - lsb (rsbbecl) h ex a ddress : 0 x n906 b it f unction t ype d efault d escription -o peration 7 rsbbec[7] rur 0 performance monitor ?receive synchronization bit error 16-bit counter? - lower byte: these reset-upon-read bits, along with that within the ?pmon receive synchronization bit error counter register msb? combine to reflect the cumulative number of instances that the receive syn - chronization bit errors has been detected by the receive e1 framer block since the last read of this register. this register contains the least significant byte of this 16-bit of the receive synchronization bit error counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rsbbec[6] rur 0 5 rsbbec[5] rur 0 4 rsbbec[4] rur 0 3 rsbbec[3] rur 0 2 rsbbec[2] rur 0 1 rsbbec[1] rur 0 0 rsbbec[0] rur 0
xrt86vl34 94 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 79: pmon r eceive f ar -e nd bl ock e rror c ounter - msb (rfebecu) h ex a ddress : 0 x n907 b it f unction t ype d efault d escription -o peration 7 rfebec[15] rur 0 performance monitor - receive far-end block error 16-bit counter - upper byte: these reset-upon-read bits, along with that within the ?pmon receive far-end block error counter register lsb? combine to reflect the cumulative number of instances that the receive far-end block errors has been detected by the receive e1 framer block since the last read of this register. this register contains the most significant byte of this 16-bit of the receive far-end block error counter. n ote : the receive far-end block error counter will increment once each time the received e-bit is set to zero. this counter is disabled during loss of sync at either the fas or crc-4 level and it will continue to count if loss of multiframe sync occurs at the cas level. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rfebec[14] rur 0 5 rfebec[13] rur 0 4 rfebec[12] rur 0 3 rfebec[11] rur 0 2 rfebec[10] rur 0 1 rfebec[9] rur 0 0 rfebec[8] rur 0 t able 80: pmon r eceive f ar e nd b lock e rror c ounter -lsb (rfebecl) h ex a ddress : 0 x n908 b it f unction t ype d efault d escription -o peration 7 rfebec[7] rur 0 performance monitor - receive far-end block error 16-bit counter - lower byte: these reset-upon-read bits, along with that within the ?pmon receive far-end block error counter register msb? combine to reflect the cumulative number of instances that the receive far-end block errors has been detected by the receive e1 framer block since the last read of this register. this register contains the least significant byte of this 16-bit of the receive far-end block error counter. n ote : the receive far-end block error counter will increment once each time the received e-bit is set to zero. this counter is disabled during loss of sync at either the fas or crc-4 level and it will continue to count if loss of multiframe sync occurs at the cas level. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 rfebec[6] rur 0 5 rfebec[5] rur 0 4 rfebec[4] rur 0 3 rfebec[3] rur 0 2 rfebec[2] rur 0 1 rfebec[1] rur 0 0 rfebec[0] rur 0
xrt86vl34 95 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 81: pmon r eceive s lip c ounter (rsc) h ex a ddress : 0 x n909 b it f unction t ype d efault d escription -o peration 7 rsc[7] rur 0 performance monitor - receive slip counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that receive slip events have been detected by the e1 framer since the last read of this register. n ote : a slip event is defined as a replication or deletion of a e1 frame by the receive slip buffer. 6 rsc[6] rur 0 5 rsc[5] rur 0 4 rsc[4] rur 0 3 rsc[3] rur 0 2 rsc[2] rur 0 1 rsc[1] rur 0 0 rsc[0] rur 0 t able 82: pmon r eceive l oss of f rame c ounter (rlfc) h ex a ddress : 0 x n90a b it f unction t ype d efault d escription -o peration 7 rlfc[7] rur 0 performance monitor - receive loss of frame counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that receive loss of frame condition have been detected by the e1 framer since the last read of this register. n ote : this counter counts once every time the loss of frame condition is declared. this counter provides the capability to measure an accumulation of short failure events. 6 rlfc[6] rur 0 5 rlfc[5] rur 0 4 rlfc[4] rur 0 3 rlfc[3] rur 0 2 rlfc[2] rur 0 1 rlfc[1] rur 0 0 rlfc[0] rur 0 t able 83: pmon r eceive c hange of f rame a lignment c ounter (rcfac) h ex a ddress : 0 x n90b b it f unction t ype d efault d escription -o peration 7 rcfac[7] rur 0 performance monitor - receive change of frame alignment counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that receive change of framing alignment have been detected by the e1 framer since the last read of this register. n ote : change of framing alignment (cofa) is declared when the newly-locked framing pattern is different from the one offered by off-line framer. 6 rcfac[6] rur 0 5 rcfac[5] rur 0 4 rcfac[4] rur 0 3 rcfac[3] rur 0 2 rcfac[2] rur 0 1 rcfac[1] rur 0 0 rcfac[0] rur 0
xrt86vl34 96 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 84: pmon lapd f rame c heck s equence e rror c ounter 1 (lfcsec1) h ex a ddress : 0 x n90c b it f unction t ype d efault d escription -o peration 7 fcsec1[7] rur 0 performance monitor - lapd 1 frame check sequence error counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that frame check sequence error have been detected by the lapd controller 1 since the last read of this register. 6 fcsec1[6] rur 0 5 fcsec1[5] rur 0 4 fcsec1[4] rur 0 3 fcsec1[3] rur 0 2 fcsec1[2] rur 0 1 fcsec1[1] rur 0 0 fcsec1[0] rur 0 t able 85: pmon prbs b it e rror c ounter msb (pbecu) h ex a ddress : 0 x n90d b it f unction t ype d efault d escription -o peration 7 prbse[15] rur 0 performance monitor - e1 prbs bit error 16-bit counter - upper byte: these reset-upon-read bits, along with that within the ?pmon e1 prbs bit error counter register lsb? combine to reflect the cumulative number of instances that the receivee1 prbs bit errors has been detected by the receive e1 framer block since the last read of this register. this register contains the most significant byte of this 16-bit of the receive e1 prbs bit error counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 prbse[14] rur 0 5 prbse[13] rur 0 4 prbse[12] rur 0 3 prbse[11] rur 0 2 prbse[10] rur 0 1 prbse[9] rur 0 0 prbse[8] rur 0 t able 86: pmon prbs b it e rror c ounter lsb (pbecl) h ex a ddress : 0 x n90e b it f unction t ype d efault d escription -o peration 7 prbse[7] rur 0 performance monitor - e1 prbs bit error 16-bit counter - lower byte: these reset-upon-read bits, along with that within the ?pmon e1 prbs bit error counter register msb? combine to reflect the cumulative number of instances that the receivee1 prbs bit errors has been detected by the receive e1 framer block since the last read of this register. this register contains the least significant byte of this 16-bit of the receive e1 prbs bit error counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 prbse[6] rur 0 5 prbse[5] rur 0 4 prbse[4] rur 0 3 prbse[3] rur 0 2 prbse[2] rur 0 1 prbse[1] rur 0 0 prbse[0] rur 0
xrt86vl34 97 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 87: pmon t ransmit s lip c ounter (tsc) h ex a ddress : 0 x n90f b it f unction t ype d efault d escription -o peration 7 txslip[7] rur 0 performance monitor - transmit slip counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that transmit slip events have been detected by the e1 framer since the last read of this register. n ote : a slip event is defined as a replication or deletion of a e1 frame by the transmit slip buffer. 6 txslip[6] rur 0 5 txslip[5] rur 0 4 txslip[4] rur 0 3 txslip[3] rur 0 2 txslip[2] rur 0 1 txslip[1] rur 0 0 txslip[0] rur 0 t able 88: pmon e xcessive z ero v iolation c ounter msb (ezvcu) h ex a ddress : 0 x n910 b it f unction t ype d efault d escription -o peration 7 ezvc[15] rur 0 performance monitor - e1 excessive zero violation 16-bit counter - upper byte: these reset-upon-read bits, along with that within the ?pmon e1 excessive zero violation counter register lsb? combine to reflect the cumulative number of instances that the receivee1 excessive zero violation has been detected by the receive e1 framer block since the last read of this register. this register contains the most significant byte of this 16-bit of the receive e1 excessive zero violation counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 ezvc[14] rur 0 5 ezvc[13] rur 0 4 ezvc[12] rur 0 3 ezvc[11] rur 0 2 ezvc[10] rur 0 1 ezvc[9] rur 0 0 ezvc[8] rur 0 t able 89: pmon e xcessive z ero v iolation c ounter lsb (ezvcl) h ex a ddress : 0 x n911 b it f unction t ype d efault d escription -o peration 7 ezvc[7] rur 0 performance monitor - e1 excessive zero violation 16-bit counter - lower byte: these reset-upon-read bits, along with that within the ?pmon e1 excessive zero violation counter register msb? combine to reflect the cumulative number of instances that the receivee1 excessive zero violation has been detected by the receive e1 framer block since the last read of this register. this register contains the least significant byte of this 16-bit of the receive e1 excessive zero violation counter. n ote : for all 16-bit wide pmon registers, user must read the msb counter first before reading the lsb counter in order to read the accurate pmon counts. to clear pmon count, user must read the msb counter first before reading the lsb counter in order to clear the pmon count. 6 ezvc[6] rur 0 5 ezvc[5] rur 0 4 ezvc[4] rur 0 3 ezvc[3] rur 0 2 ezvc[2] rur 0 1 ezvc[1] rur 0 0 ezvc[0] rur 0
xrt86vl34 98 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 90: pmon f rame c heck s equence e rror c ounter 2 (lfcsec2) h ex a ddress : 0 x n91c b it f unction t ype d efault d escription -o peration 7 fcsec2[7] rur 0 performance monitor - lapd 2 frame check sequence error counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that frame check sequence error have been detected by the lapd controller 2 since the last read of this register. 6 fcsec2[6] rur 0 5 fcsec2[5] rur 0 4 fcsec2[4] rur 0 3 fcsec2[3] rur 0 2 fcsec2[2] rur 0 1 fcsec2[1] rur 0 0 fcsec2[0] rur 0 t able 91: pmon f rame c heck s equence e rror c ounter 3 (lfcsec3) h ex a ddress : 0 x n92c b it f unction t ype d efault d escription -o peration 7 fcsec3[7] rur 0 performance monitor - lapd 3 frame check sequence error counter (8-bit counter) these reset-upon-read bit fields reflect the cumulative number of instances that frame check sequence error have been detected by the lapd controller 3 since the last read of this register. 6 fcsec3[6] rur 0 5 fcsec3[5] rur 0 4 fcsec3[4] rur 0 3 fcsec3[3] rur 0 2 fcsec3[2] rur 0 1 fcsec3[1] rur 0 0 fcsec3[0] rur 0
xrt86vl34 99 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 92: b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x nb00 b it f unction t ype d efault d escription -o peration 7 sa6 ro 0 sa6 block interrupt status this bit indicates whether or not the sa 6 block has an interrupt request awaiting service. 0 - indicates no outstanding sa 6 block interrupt request is awaiting service 1 - indicates the sa 6 block has an interrupt request awaiting ser - vice. interrupt service routine should branch to the interrupt source and read the sa6 block interrupt status register (address 0xnb0c) to clear the interrupt n ote : this bit will be reset to 0 after the microprocessor has performed a read to the sa6 interrupt status register 6 reserved for t1 mode only 5 rxclklos ro 0 loss of recovered clock interrupt status this bit indicates whether or not the e1 receive framer is currently declaring the "loss of recovered clock" interrupt. 0 = indicates that the e1 receive framer block is not currently declaring the "loss of recovered clock" interrupt. 1 = indicates that the e1 receive framer block is currently declar - ing the "loss of recovered clock" interrupt. n ote : this bit is only active if the clock loss detection feature is enabled (register - 0xn100) 4 onesec ro 0 one second interrupt status this bit indicates whether or not the e1 receive framer block is cur - rently declaring the "one second" interrupt. 0 = indicates that the e1 receive framer block is not currently declaring the "one second" interrupt. 1 = indicates that the e1 receive framer block is currently declar - ing the "one second" interrupt. 3 hdlc ro 0 hdlc block interrupt status this bit indicates whether or not the hdlc block has any interrupt request awaiting service. 0 = indicates no outstanding hdlc block interrupt request is await - ing service 1 = indicates hdlc block has an interrupt request awaiting service. interrupt service routine should branch to the interrupt source and read the corresponding data link status registers (address 0xnb06, 0xnb16, 0xnb26, 0xnb10, 0xnb18, 0xnb28) to clear the interrupt. n ote : this bit will be reset to 0 after the microprocessor has performed a read to the corresponding data link status registers that generated the interrupt.
xrt86vl34 100 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 2 slip ro 0 slip buffer block interrupt status this bit indicates whether or not the slip buffer block has any out - standing interrupt request awaiting service. 0 = indicates no outstanding slip buffer block interrupt request is awaiting service 1 = indicates slip buffer block has an interrupt request awaiting ser - vice. interrupt service routine should branch to the interrupt source and read the slip buffer interrupt status register (address 0xnb08) to clear the interrupt n ote : this bit will be reset to 0 after the microprocessor has performed a read to the slip buffer interrupt status register. 1 alarm ro 0 alarm & error block interrupt status this bit indicates whether or not the alarm & error block has any outstanding interrupt request awaiting service. 0 = indicates no outstanding interrupt request is awaiting service 1 = indicates the alarm & error block has an interrupt request await - ing service. interrupt service routine should branch to the interrupt source and read the corresponding alarm and error status registers (address 0xnb02, 0xnb0e, 0xnb40) to clear the interrupt. n ote : this bit will be reset to 0 after the microprocessor has performed a read to the corresponding alarm & error interrupt status register that generated the interrupt. 0 e1 frame ro 0 e1 framer block interrupt status this bit indicates whether or not the e1 framer block has any out - standing interrupt request awaiting service. 0 = indicates no outstanding interrupt request is awaiting service. 1 = indicates the e1 framer block has an interrupt request awaiting service. interrupt service routine should branch to the interrupt source and read the e1 framer status register (address 0xnb04) to clear the interrupt n ote : this bit will be reset to 0 after the microprocessor has performed a read to the e1 framer interrupt status register. t able 92: b lock i nterrupt s tatus r egister (bisr) h ex a ddress : 0 x nb00 b it f unction t ype d efault d escription -o peration
xrt86vl34 101 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 93: b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x nb01 b it f unction t ype d efault d escription -o peration 7 sa6_enb r/w 0 sa6 block interrupt enable this bit permits the user to either enable or disable the sa 6 block for interrupt generation. if the user writes a ?0? to this register bit and disables the sa 6 block for interrupt generation, then all sa 6 interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, the sa6 block interrupt at the ?block level? will be enabled. however, the individual sa 6 inter - rupts at the ?source level? still need to be enabled in order to gener - ate that particular interrupt to the interrupt pin. 0 - disables all sa6 block interrupt within the device. 1 - enables the sa6 interrupt at the ?block-level?. 6 reserved for t1 mode only 5 rxclkloss r/w 0 loss of recovered clock interrupt enable this bit permits the user to either enable or disable the loss of recovered clock interrupt for interrupt generation. 0 - disables the loss of recovered clock interrupt within the device. 1 - enables the loss of recovered clock interrupt at the ?source- level?. 4 onesec_enb r/w 0 one second interrupt enable this bit permits the user to either enable or disable the one second interrupt for interrupt generation. 0 - disables the one second interrupt within the device. 1 - enables the one second interrupt at the ?source-level?. 3 hdlc_enb r/w 0 hdlc block interrupt enable this bit permits the user to either enable or disable the hdlc block for interrupt generation. if the user writes a ?0? to this register bit and disables the hdlc block for interrupt generation, then all hdlc interrupts will be dis - abled for interrupt generation. if the user writes a ?1? to this register bit, the hdlc block interrupt at the ?block level? will be enabled. however, the individual hdlc interrupts at the ?source level? still need to be enabled in order to generate that particular interrupt to the interrupt pin. 0 - disables all sa6 block interrupt within the device. 1 - enables the sa6 interrupt at the ?block-level?. 2 slip_enb r/w 0 slip buffer block interrupt enable this bit permits the user to either enable or disable the slip buffer block for interrupt generation. if the user writes a ?0? to this register bit and disables the slip buffer block for interrupt generation, then all slip buffer interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, the slip buffer block inter - rupt at the ?block level? will be enabled. however, the individual slip buffer interrupts at the ?source level? still need to be enabled in order to generate that particular interrupt to the interrupt pin. 0 - disables all slip buffer block interrupt within the device. 1 - enables the slip buffer interrupt at the ?block-level?.
xrt86vl34 102 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 alarm_enb r/w 0 alarm & error block interrupt enable this bit permits the user to either enable or disable the alarm & error block for interrupt generation. if the user writes a ?0? to this register bit and disables the alarm & error block for interrupt generation, then all alarm & error interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, the alarm & error block interrupt at the ?block level? will be enabled. however, the individual alarm & error interrupts at the ?source level? still need to be enabled in order to generate that particular interrupt to the interrupt pin. 0 - disables all alarm & error block interrupt within the device. 1 - enables the alarm & error interrupt at the ?block-level?. 0 e1frame_enb r/w 0 e1 framer block enable this bit permits the user to either enable or disable the e1 framer block for interrupt generation. if the user writes a ?0? to this register bit and disables the e1 framer block for interrupt generation, then all e1 framer interrupts will be disabled for interrupt generation. if the user writes a ?1? to this register bit, the e1 framer block inter - rupt at the ?block level? will be enabled. however, the individual e1 framer interrupts at the ?source level? still need to be enabled in order to generate that particular interrupt to the interrupt pin. 0 - disables all e1 framer block interrupt within the device. 1 - enables the e1 framer interrupt at the ?block-level?. t able 93: b lock i nterrupt e nable r egister (bier) h ex a ddress : 0 x nb01 b it f unction t ype d efault d escription -o peration
xrt86vl34 103 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 94: a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x nb02 b it f unction t ype d efault d escription -o peration 7 rx oof state ro 0 receive out of frame defect state this read-only bit indicates whether or not the receive e1 framer block is currently declaring the ?out of frame? defect condition within the incom - ing e1 data-stream, as described below. out of frame defect condition is declared when ?fasc? number of consecu - tive errored fas patterns are detected, where ?fasc? indicates the loss of fas alignment criteria in the framing control register (0xn10b), bit 2-0. 0 ? the receive e1 framer block is not currently declaring the ?out of frame? defect condition. 1 ? the receive e1 framer block is currently declaring the ?out of frame? defect condition. 6 rxais state ro 0 receive alarm indication status defect state this read-only bit indicates whether or not the receive e1 framer block is currently declaring the ais defect condition within the incoming e1 data- stream, as described below. ais defect is declared when ais condition persists for 250 microseconds (2 frames). ais defect is cleared when more than 2 zeros are detected in two consecutive frames (250us) 0 ? the receive e1 framer block is not currently declaring the ais defect condition. 1 ? the receive e1 framer block is currently declaring the ais defect con - dition. 5 rxmyel status rur/ wc 0 change of cas multiframe yellow alarm interrupt status . this reset-upon-read bit field indicates whether or not the cas multiframe yellow alarm interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the cas multiframe yellow alarm. 2. whenever the receive e1 framer block clears the cas multiframe yellow alarm cas multiframe yellow alarm is declared whenever the received ?y? bit in time slot 16 of frame 0 is set to ?1?. 0 = indicates that the ?change of cas multiframe yellow alarm? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change of cas multiframe yellow alarm? interrupt has occurred since the last read of this register. 4 los state ro 0 framer receive loss of signal (los) state this read-only bit indicates whether or not the receive e1 framer is cur - rently declaring the loss of signal (los) condition within the incoming ds1 data-stream, as described below los defect is declared when los condition persists for 175 consecutive bits. los defect is cleared when los condition is absent or when the received signal reaches a 12.5% ones density for 175 consecutive bits. 0 = the receive ds1 framer block is not currently declaring the loss of signal (los) condition. 1 = the receive ds1 framer block is currently declaring the loss of signal (los) condition.
xrt86vl34 104 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 lcv int status rur/ wc 0 line code violation interrupt status . this reset-upon-read bit field indicates whether or not the receive e1 liu block has detected a line code violation interrupt since the last read of this register. 0 = indicates that the line code violation interrupt has not occurred since the last read of this register. 1 = indicates that the line code violation interrupt has occurred since the last read of this register. 2 rx oof state change rur/ wc 0 change in out of frame defect condition interrupt status . this reset-upon-read bit field indicates whether or not the ?change in receive out of frame defect condition? interrupt has occurred since the last read of this register. out of frame defect condition is declared when ?fasc? number of consecu - tive errored fas patterns are detected, where ?fasc? indicates the loss of fas alignment criteria in the framing control register (0xn10b), bit 2-0. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the out of frame defect condition. 2. whenever the receive e1 framer block clears the out of frame defect condition 0 = indicates that the ?change in receive out of frame defect condition? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in receive out of frame defect condition? interrupt has occurred since the last read of this register 1 rxais state change rur/ wc 0 change in receive ais condition interrupt status . this reset-upon-read bit field indicates whether or not the ?change in receive ais condition? interrupt has occurred since the last read of this reg - ister. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the ais condition. 2. whenever the receive e1 framer block clears the ais condition 0 = indicates that the ?change in receive ais condition? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in receive ais condition? interrupt has occurred since the last read of this register t able 94: a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x nb02 b it f unction t ype d efault d escription -o peration
xrt86vl34 105 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 0 rxyel state change rur/ wc 0 change in receive yellow alarm interrupt status. this reset-upon-read bit field indicates whether or not the ?change in receive yellow alarm condition? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the yellow alarm condition. 2. whenever the receive e1 framer block clears the yellow alarm condition 0 = indicates that the ?change in receive yellow alarm condition? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in receive yellow alarm condition? interrupt has occurred since the last read of this register t able 94: a larm & e rror i nterrupt s tatus r egister (aeisr) h ex a ddress : 0 x nb02 b it f unction t ype d efault d escription -o peration
xrt86vl34 106 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 95: a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x nb03 b it f unction t ype d efault d escription -o peration 7 rx_yel_state ro 0 receive yellow alarm state this read-only bit indicates whether or not the receive e1 framer block is currently declaring the yellow alarm condition within the incoming e1 data-stream, as described below. yellow alarm or remote alarm indication (rai) is declared when the ?a? bit of two consecutive non-fas frames is set to ?1?, which is equivalent to tak - ing 375us to declare a rai condition. yellow alarm is cleared when the ?a? bit of two consecutive non-fas frames is set to 0, which is equivalent to taking 375us to clear a rai condition. 0 ? the receive e1 framer block is not currently declaring the yellow alarm condition. 1 ? the receive e1 framer block is currently declaring the yellow alarm condition. 6 reserved - - reserved 5 rxmyel enb r/w 0 change of cas multiframe yellow alarm interrupt enable . this bit permits the user to either enable or disable the ?change in cas multiframe yellow alarm? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. the instant that the receive e1 framer block declares cas multiframe yellow alarm. 2. the instant that the receive e1 framer block clears the cas multiframe yellow alarm. 0 ? disables the ?change in cas multiframe yellow alarm? interrupt. 1 ? enables the ?change in cas multiframe yellow alarm? interrupt. 4 - r/w 0 this bit should be set to?0? for proper operation. 3 lcv enb r/w 0 line code violation interrupt enable this bit permits the user to either enable or disable the ?line code viola - tion? interrupt within the xrt86vl34 device. if the user enables this inter - rupt, then the receive e1 framer block will generate an interrupt when line code violation is detected. 0 = disables the interrupt generation when line code violation is detected. 1 = enables the interrupt generation when line code violation is detected. 2 rxoof enb r/w 0 change in out of frame defect condition interrupt enable this bit permits the user to either enable or disable the ?change in out of frame defect condition? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. the instant that the receive e1 framer block declares the out of frame defect condition. 2. the instant that the receive e1 framer block clears the out of frame defect condition. 0 ? disables the ?change in out of frame defect condition? interrupt. 1 ? enables the ?change in out of frame defect condition? interrupt.
xrt86vl34 107 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 rxais enb r/w 0 change in ais condition interrupt enable this bit permits the user to either enable or disable the ?change in ais condition? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. the instant that the receive e1 framer block declares the ais condition. 2. the instant that the receive e1 framer block clears the ais condition. 0 ? disables the ?change in ais condition? interrupt. 1 ? enables the ?change in ais condition? interrupt. 0 rxyel enb r/w 0 change in yellow alarm condition interrupt enable this bit permits the user to either enable or disable the ?change in yellow alarm condition? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. the instant that the receive e1 framer block declares the yellow alarm condition. 2. the instant that the receive e1 framer block clears the yellow alarm condition. 0 ? disables the ?change in yellow alarm condition? interrupt. 1 ? enables the ?change in yellow alarm condition? interrupt. t able 95: a larm & e rror i nterrupt e nable r egister (aeier) h ex a ddress : 0 x nb03 b it f unction t ype d efault d escription -o peration
xrt86vl34 108 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 t able 96: f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x nb04 b it f unction t ype d efault d escription -o peration 7 comfa status rur/ wc 0 change of cas multiframe alignment interrupt status this reset-upon-read bit field indicates whether or not the ?change of cas multiframe alignment? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the ?loss of cas multiframe alignment?. 2. whenever the receive e1 framer block clears the ?loss of cas multiframe alignment? loss cas multiframe alignment is declared when the ?casc? number of consecutive cas multiframe alignment signals have been received in error, where casc sets the criteria for loss of cas multiframe. casc can ben programmed through framing control register (fcr - address 0xn10b, bit 6-5) 0 = indicates that the ?change of cas multiframe alignment? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change of cas multiframe alignment? interrupt has occurred since the last read of this register. n otes : this bit only has meaning when channel associated signaling (cas) is enabled. 6 nbit status rur/ wc 0 change in national bits interrupt status this reset-upon-read bit field indicates whether or not the ?change in national bits? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt whenever any one of the national bits (sa4-sa8) within the incoming non-fas e1 frames has changed. 0 = indicates that the ?change in national bits? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in national bits? interrupt has occurred since the last read of this register. 5 sig status rur/ wc 0 change in cas signaling bits interrupt status this reset-upon-read bit field indicates whether or not the ?change in cas signaling bits? interrupt has occurred since the last read of this regis - ter. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt whenever any one of the four signaling bits values (a,b,c,d) has changed in any one of the 30 channels within the incoming e1 frames. users can read the signaling change registers (address 0xn10d-0xn110) to determine which signalling channel has changed. 0 = indicates that the ?change in cas signaling bits? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in cas signaling bits? interrupt has occurred since the last read of this register. n ote : this bit only has meaning when channel associated signaling (cas) is enabled.
xrt86vl34 109 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 4 cofa status rur/ wc 0 change of fas framing alignment (cofa) interrupt status this reset-upon-read bit field indicates whether or not the ?change of fas framing alignment? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt whenever the receive e1 framer block detects a change of fas framing alignment signal (e.g., the fas bits have appeared to move to a different location within the incoming e1 data stream). 0 = indicates that the ?change of fas framing alignment (cofa)? inter - rupt has not occurred since the last read of this register. 1 = indicates that the ?change of fas framing alignment (cofa)? inter - rupt has occurred since the last read of this register. 3 oof status rur/ wc 0 change in out of frame defect condition interrupt status . this reset-upon-read bit field indicates whether or not the ?change in receive out of frame defect condition? interrupt has occurred since the last read of this register. out of frame defect condition is declared when ?fasc? number of consec - utive errored fas patterns are detected, where ?fasc? indicates the loss of fas alignment criteria in the framing control register (0xn10b), bit 2- 0. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the out of frame defect condition. 2. whenever the receive e1 framer block clears the out of frame defect condition 0 = indicates that the ?change in receive out of frame defect condition? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in receive out of frame defect condition? interrupt has occurred since the last read of this register 2 fmd status rur/ wc 0 frame mimic detection interrupt status this reset-upon-read bit field indicates whether or not the ?frame mimic detection? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt whenever the receive e1 framer block detects the presence of frame mimic bits (i.e., the payload bits have appeared to mimic the framing pattern within the incoming e1 data stream). 0 = indicates that the ?frame mimic detection? interrupt has not occurred since the last read of this register. 1 = indicates that the ?frame mimic detection? interrupt has occurred since the last read of this register. t able 96: f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x nb04 b it f unction t ype d efault d escription -o peration
xrt86vl34 110 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 sync error status rur/ wc 0 crc-4 error interrupt status. this reset-upon-read bit field indicates whether or not the ?crc-4 error? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt whenever the receive e1 framer block detects a crc-4 error within the incoming e1 sub-multiframe. 0 = indicates that the ?crc-4 error? interrupt has not occurred since the last read of this register. 1 = indicates that the ?crc-4 error? interrupt has occurred since the last read of this register. 0 framing error sta - tus rur/ wc 0 framing error interrupt status this reset-upon-read bit field indicates whether or not a ?framing error? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt whenever the receive e1 framer block detects one or more framing alignment bit error within the incoming e1 data stream. 0 = indicates that the ?framing error? interrupt has not occurred since the last read of this register. 1 = indicates that the ?framing error? interrupt has occurred since the last read of this register. n ote : this bit doesn't not necessarily indicate that synchronization has been lost. t able 96: f ramer i nterrupt s tatus r egister (fisr) h ex a ddress : 0 x nb04 b it f unction t ype d efault d escription -o peration
xrt86vl34 111 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 t able 97: f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 x nb05 b it f unction t ype d efault d escription -o peration 7 comfa enb r/w 0 change in cas multiframe alignment interrupt enable this bit permits the user to either enable or disable the ?change in cas multiframe alignment? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. the instant that the receive e1 framer block declares the loss of cas multiframe alignment condition. 2. the instant that the receive e1 framer block clears the loss of cas multiframe alignment condition. 0 ? disables the ?change in cas multiframe alignment? interrupt. 1 ? enables the ?change in cas multiframe alignment? interrupt. 6 nbit enb r/w 0 change in national bits interrupt enable this bit permits the user to either enable or disable the ?change in national bits? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt when it detects a change in the national bits (sa4-sa8) within the channel. 0 = disables the change in national bits interrupt 1 - enables the change in national bits interrupt 5 sig enb r/w 0 change in cas signaling bits interrupt enable this bit permits the user to either enable or disable the ?change in cas signaling bits? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt when it detects a change in the any four signaling bits (a,b,c,d) in any one of the 30 signaling channels. users can read the signaling change regis - ters (address 0xn10d-0xn110) to determine which signalling channel has changed state. 0 = disables the change in signaling bits interrupt 1 - enables the change in signaling bits interrupt n ote : this bit has no meaning when channel associated signaling is disabled. 4 cofa enb r/w 0 change of fas framing alignment (cofa) interrupt enable this bit permits the user to either enable or disable the ?change in fas framing alignment (cofa)? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt when it detects a change of fas framing alignment signal (e.g., the fas bits have appeared to move to a different location within the incoming e1 data stream). 0 ? disables the ?change of fas framing alignment (cofa)? interrupt. 1 ? enables the ?change of fas framing alignment (cofa)? interrupt.
xrt86vl34 112 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 oof enb r/w 0 change in out of frame defect condition interrupt enable this bit permits the user to either enable or disable the ?change in out of frame defect condition? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. the instant that the receive e1 framer block declares the out of frame defect condition. 2. the instant that the receive e1 framer block clears the out of frame defect condition. 0 ? disables the ?change in out of frame defect condition? interrupt. 1 ? enables the ?change in out of frame defect condition? interrupt. 2 fmd enb r/w 0 frame mimic detection interrupt enable this bit permits the user to either enable or disable the ?frame mimic detection? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt when it detects the presence of frame mimic bits (i.e., the payload bits have appeared to mimic the framing bit pattern within the incoming e1 data stream). 0 ? disables the ?frame mimic detection? interrupt. 1 ? enables the ?frame mimic detection? interrupt. 1 se_enb r/w 0 synchronization bit (crc-4) error interrupt enable this bit permits the user to either enable or disable the ?crc-4 error detection? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt when it detects a crc-4 error within the incoming e1 sub-multiframe. 0 ? disable the ?crc-4 error detection? interrupt. 1 ? enable the ?crc-4 error detection? interrupt. 0 fe_enb r/w 0 framing bit error interrupt enable this bit permits the user to either enable or disable the ?framing alignment bit error detection? interrupt, within the xrt86vl34 device. if the user enables this interrupt, then the receive e1 framer block will generate an interrupt when it detects one or more framing alignment bit error within the incoming e1 data stream. 0 ? disable the ?framing alignment bit error detection? interrupt. 1 ? enable the ?framing alignment bit error detection? interrupt. n ote : detecting framing alignment bit error doesn't not necessarily indicate that synchronization has been lost. t able 97: f ramer i nterrupt e nable r egister (fier) h ex a ddress : 0 x nb05 b it f unction t ype d efault d escription -o peration
xrt86vl34 113 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 98: d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 x nb06 b it f unction t ype d efault d escription -o peration 7 msg type ro 0 hdlc1 message type identifier this read only bit indicates the type of data link message received by receive hdlc 1 controller. two types of data link mes - sages are supported within the xrt86vl34 device: message ori - ented signaling (mos) or bit-oriented signalling (bos). 0 = indicates bit-oriented signaling (bos) type data link message is received 1 = indicates message oriented signaling (mos) type data link message is received 6 txsot rur/ wc 0 transmit hdlc1 controller start of transmission (txsot) interrupt status this reset-upon-read bit indicates whether or not the ?transmit hdlc1 controller start of transmission (txsot) ?interrupt has occurred since the last read of this register. transmit hdlc1 con - troller will declare this interrupt when it has started to transmit a data link message. for sending large hdlc messages, start loading the next available buffer once this interrupt is detected. 0 = transmit hdlc1 controller start of transmission (txsot) inter - rupt has not occurred since the last read of this register 1 = transmit hdlc1 controller start of transmission interrupt (txsot) has occurred since the last read of this register. 5 rxsot rur/ wc 0 receive hdlc1 controller start of reception (rxsot) interrupt status this reset-upon-read bit indicates whether or not the receive hdlc1 controller start of reception (rxsot) interrupt has occurred since the last read of this register. receive hdlc1 con - troller will declare this interrupt when it has started to receive a data link message. 0 = receive hdlc1 controller start of reception (rxsot) interrupt has not occurred since the last read of this register 1 = receive hdlc1 controller start of reception (rxsot) interrupt has occurred since the last read of this register 4 txeot rur/ wc 0 transmit hdlc1 controller end of transmission (txeot) inter - rupt status this reset-upon-read bit indicates whether or not the transmit hdlc1 controller end of transmission (txeot) interrupt has occurred since the last read of this register. transmit hdlc1 con - troller will declare this interrupt when it has completed its transmis - sion of a data link message. for sending large hdlc messages, it is critical to load the next available buffer before this interrupt occurs. 0 = transmit hdlc1 controller end of transmission (txeot) inter - rupt has not occurred since the last read of this register 1 = transmit hdlc1 controller end of transmission (txeot) inter - rupt has occurred since the last read of this register
xrt86vl34 114 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 rxeot rur/ wc 0 receive hdlc1 controller end of reception (rxeot) interrupt status this reset-upon-read bit indicates whether or not the receive hdlc1 controller end of reception (rxeot) interrupt has occurred since the last read of this register. receive hdlc1 controller will declare this interrupt once it has completely received a full data link message, or once the buffer is full. 0 = receive hdlc1 controller end of reception (rxeot) interrupt has not occurred since the last read of this register 1 = receive hdlc1 controller end of reception (rxeot) interrupt has occurred since the last read of this register 2 fcs error rur/ wc 0 fcs error interrupt status this reset-upon-read bit indicates whether or not the fcs error interrupt has occurred since the last read of this register. receive hdlc1 controller will declare this interrupt when it has detected the fcs error in the most recently received data link message. 0 = fcs error interrupt has not occurred since the last read of this register 1 = fcs error interrupt has occurred since the last read of this regis - ter 1 rx abort rur/ wc 0 receipt of abort sequence interrupt status this reset-upon-read bit indicates whether or not the receipt of abort sequence interrupt has occurred since last read of this regis - ter. receive hdlc1 controller will declare this interrupt if it detects the abort sequence (i.e. a string of seven (7) consecutive 1?s) in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occurred since last read of this register 1 = receipt of abort sequence interrupt has occurred since last read of this register 0 rxidle rur/ wc 0 receipt of idle sequence interrupt status this reset-upon-read bit indicates whether or not the receipt of idle sequence interrupt has occurred since the last read of this reg - ister. the receive hdlc1 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. if rxidle "and" rxeot occur together, then the entire hdlc message has been received. 0 = receipt of idle sequence interrupt has not occurred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 98: d ata l ink s tatus r egister 1 (dlsr1) h ex a ddress : 0 x nb06 b it f unction t ype d efault d escription -o peration
xrt86vl34 115 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 99: d ata l ink i nterrupt e nable r egister 1 (dlier1) h ex a ddress : 0 x nb07 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc1 controller start of transmission (txsot) interrupt enable this bit enables or disables the ?transmit hdlc1 controller start of transmission (txsot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit hdlc1 controller will generate an interrupt when it has started to transmit a data link message. 0 = disables the transmit hdlc1 controller start of transmission (txsot) interrupt. 1 = enables the transmit hdlc1 controller start of transmission (txsot) interrupt. 5 rxsot enb r/w 0 receive hdlc1 controller start of reception (rxsot) interrupt enable this bit enables or disables the ?receive hdlc1 controller start of reception (rxsot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc1 controller will generate an interrupt when it has started to receive a data link message. 0 = disables the receive hdlc1 controller start of reception (rxsot) interrupt. 1 = enables the receive hdlc1 controller start of reception (rxsot) interrupt. 4 txeot enb r/w 0 transmit hdlc1 controller end of transmission (txeot) inter - rupt enable this bit enables or disables the ?transmit hdlc1 controller end of transmission (txeot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit hdlc1 controller will generate an interrupt when it has finished transmitting a data link message. 0 = disables the transmit hdlc1 controller end of transmission (txeot) interrupt. 1 = enables the transmit hdlc1 controller end of transmission (txeot) interrupt. 3 rxeot enb r/w 0 receive hdlc1 controller end of reception (rxeot) interrupt enable this bit enables or disables the ?receive hdlc1 controller end of reception (rxeot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc1 controller will generate an interrupt when it has finished receiving a complete data link message. 0 = disables the receive hdlc1 controller end of reception (rxeot) interrupt. 1 = enables the receive hdlc1 controller end of reception (rxeot) interrupt.
xrt86vl34 116 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 2 fcs err enb r/w 0 fcs error interrupt enable this bit enables or disables the ?received fcs error ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc1 controller will generate an interrupt when it has detected the fcs error within the incoming data link message. 0 = disables the ?receive fcs error? interrupt. 1 = enables the ?receive fcs error? interrupt. 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable this bit enables or disables the ?receipt of abort sequence? inter - rupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc1 controller will generate an interrupt when it has detected the abort sequence (i.e. a string of seven (7) consecutive 1?s) within the incoming data link channel. 0 = disables the ?receipt of abort sequence? interrupt. 1 = enables the ?receipt of abort sequence? interrupt. 0 rxidle enb r/w 0 receipt of idle sequence interrupt enable this bit enables or disables the ?receipt of idle sequence? interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc1 controller will generate an interrupt when it has detected the idle sequence octet (i.e. 0x7e) within the incoming data link channel. 0 = disables the ?receipt of idle sequence? interrupt. 1 = enables the ?receipt of idle sequence? interrupt. t able 99: d ata l ink i nterrupt e nable r egister 1 (dlier1) h ex a ddress : 0 x nb07 b it f unction t ype d efault d escription -o peration
xrt86vl34 117 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 100: s lip b uffer i nterrupt s tatus r egister (sbisr) h ex a ddress : 0 x nb08 b it f unction t ype d efault d escription -o peration 7 txsb_full rur/ wc 0 transmit slip buffer full interrupt status this reset-upon-read bit indicates whether or not the transmit slip buffer full interrupt has occurred since the last read of this register. the transmit slip buffer full interrupt is declared when the transmit slip buffer is filled. if the transmit slip buffer is full and a write operation occurs, then a full frame of data will be deleted, and this interrupt bit will be set to ?1?. 0 = indicates that the transmit slip buffer full interrupt has not occurred since the last read of this register. 1 = indicates that the transmit slip buffer full interrupt has occurred since the last read of this register. 6 txsb_empt rur/ wc 0 transmit slip buffer empty interrupt status this reset-upon-read bit indicates whether or not the transmit slip buffer empty interrupt has occurred since the last read of this register. the transmit slip buffer empty interrupt is declared when the transmit slip buffer is emptied. if the transmit slip buffer is emptied and a read opera - tion occurs, then a full frame of data will be repeated, and this interrupt bit will be set to ?1?. 0 = indicates that the transmit slip buffer empty interrupt has not occurred since the last read of this register. 1 = indicates that the transmit slip buffer empty interrupt has occurred since the last read of this register. 5 txsb_slip rur/ wc 0 transmit slip buffer slips interrupt status this reset-upon-read bit indicates whether or not the transmit slip buffer slips interrupt has occurred since the last read of this register. the transmit slip buffer slips interrupt is declared when the transmit slip buffer is either filled or emptied. this interrupt bit will be set to ?1? in either one of these two conditions: 1. if the transmit slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and this interrupt bit will be set to ?1?. 2. if the transmit slip buffer is full and a write operation occurs, then a full frame of data will be deleted, and this interrupt bit will be set to ?1?. 0 = indicates that the transmit slip buffer slips interrupt has not occurred since the last read of this register. 1 = indicates that the transmit slip buffer slips interrupt has occurred since the last read of this register. n ote : users still need to read the transmit slip buffer empty interrupt (bit 6 of this register) or the transmit slip buffer full interrupts (bit 7 of this register) to determine whether transmit slip buffer empties or fills.
xrt86vl34 118 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 4 cas sync ro 0 cas multiframe alignment is in sync this read only bit field indicates whether or not the e1 receive framer block is declaring cas multiframe alignment lock status. the e1 receive framer block will declare the cas multiframe alignment lock status according to the cas multiframe alignment algorithm as described in the framing select register (fsr - address 0xn107). the e1 receive framer block will declare the cas multiframe alignment loss of lock status when casc number of consecutive cas multi - frame alignment signals have been received in error, where casc sets the loss of cas multiframe alignment criteria, as described in the fram - ing control register (fcr - address 0xn10b). 0 = indicates that the e1 receive framer block is currently declaring cas multiframe loss of lock status 1 = indicates that the e1 receive framer block is currently declaring cas multiframe lock status n ote : in e1 mode, this bit has no meaning if channel associated signaling is disabled. 3 crcmlock ro 0 crc multiframe is in sync this read only bit field indicates whether or not the e1 receive framer block is declaring the e1 crc multiframe alignment lock status. the e1 receive framer declares the crc multiframe alignment lock status according to the crc multiframe alignment declaration criteria which can be selected in the framing select register (fsr - address 0xn107) the e1 receive framer declares the crc multiframe alignment loss of lock status according to the loss crc multiframe alignment criteria selected in the framing control register (fcr - address 0xn10b) 0 = indicates that the e1 receive framer is currently declaring e1 crc multiframe alignment loss of lock status 0 = indicates that the e1 receive framer is currently declaring e1 multi - frame alignment lock status n ote : in e1 mode, this bit has no meaning if crc multiframe alignment is disabled. 2 rxsb_full rur/ wc 0 receive slip buffer full interrupt status this reset-upon-read bit indicates whether or not the receive slip buffer full interrupt has occurred since the last read of this register. the receive slip buffer full interrupt is declared when the receive slip buffer is filled. if the receive slip buffer is full and a write operation occurs, then a full frame of data will be deleted, and this interrupt bit will be set to ?1?. 0 = indicates that the receive slip buffer full interrupt has not occurred since the last read of this register. 1 = indicates that the receive slip buffer full interrupt has occurred since the last read of this register. t able 100: s lip b uffer i nterrupt s tatus r egister (sbisr) h ex a ddress : 0 x nb08 b it f unction t ype d efault d escription -o peration
xrt86vl34 119 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 rxsb_empt rur/ wc 0 receive slip buffer empty interrupt status this reset-upon-read bit indicates whether or not the receive slip buffer empty interrupt has occurred since the last read of this register. the receive slip buffer empty interrupt is declared when the receive slip buffer is emptied. if the receive slip buffer is emptied and a read opera - tion occurs, then a full frame of data will be repeated, and this interrupt bit will be set to ?1?. 0 = indicates that the receive slip buffer empty interrupt has not occurred since the last read of this register. 1 = indicates that the receive slip buffer empty interrupt has occurred since the last read of this register. 0 rxsb_slip rur/ wc 0 receive slip buffer slips interrupt status this reset-upon-read bit indicates whether or not the receive slip buffer slips interrupt has occurred since the last read of this register. the receive slip buffer slips interrupt is declared when the receive slip buffer is either filled or emptied. this interrupt bit will be set to ?1? in either one of these two conditions: 1. if the receive slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and this interrupt bit will be set to ?1?. 2. if the receive slip buffer is full and a write operation occurs, then a full frame of data will be deleted, and this interrupt bit will be set to ?1?. 0 = indicates that the receive slip buffer slips interrupt has not occurred since the last read of this register. 1 = indicates that the receive slip buffer slips interrupt has occurred since the last read of this register. n ote : users still need to read the receive slip buffer empty interrupt (bit 1 of this register) or the receive slip buffer full interrupts (bit 2 of this register) to determine whether transmit slip buffer empties or fills. t able 100: s lip b uffer i nterrupt s tatus r egister (sbisr) h ex a ddress : 0 x nb08 b it f unction t ype d efault d escription -o peration
xrt86vl34 120 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 101: s lip b uffer i nterrupt e nable r egister (sbier) h ex a ddress : 0 x nb09 b it f unction t ype d efault d escription -o peration 7 txfull_enb r/w 0 transmit slip buffer full interrupt enable this bit enables or disables the transmit slip buffer full interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit slip buffer full interrupt is declared when the transmit slip buffer is filled. if the transmit slip buffer is full and a write opera - tion occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ?1?. 0 = disables the transmit slip buffer full interrupt when the trans - mit slip buffer fills 1 - enables the transmit slip buffer full interrupt when the transmit slip buffer fills. 6 txempt_enb r/w 0 transmit slip buffer empty interrupt enable this bit enables or disables the transmit slip buffer empty interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit slip buffer empty interrupt is declared when the transmit slip buffer is emptied. if the transmit slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and the interrupt status bit will be set to ?1?. 0 = disables the transmit slip buffer empty interrupt when the transmit slip buffer empties 1 - enables the transmit slip buffer empty interrupt when the trans - mit slip buffer empties. 5 txslip_enb r/w 0 transmit slip buffer slips interrupt enable this bit enables or disables the transmit slip buffer slips interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit slip buffer slips interrupt is declared when either the trans - mit slip buffer is filled or emptied. if the transmit slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and the interrupt status bit will be set to ?1?. the interrupt status bit will be set to ?1? in either one of these two conditions: 1. if the transmit slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and this interrupt bit will be set to ?1?. 2. if the transmit slip buffer is full and a write operation occurs, then a full frame of data will be deleted, and this interrupt bit will be set to ?1?. 0 = disables the transmit slip buffer slips interrupt when the trans - mit slip buffer empties or fills 1 - enables the transmit slip buffer slips interrupt when the trans - mit slip buffer empties or fills. 4-3 reserved - - reserved
xrt86vl34 121 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 rxfull_enb r/w 0 receive slip buffer full interrupt enable this bit enables or disables the receive slip buffer full interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive slip buffer full interrupt is declared when the receive slip buffer is filled. if the receive slip buffer is full and a write opera - tion occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ?1?. 0 = disables the receive slip buffer full interrupt when the transmit slip buffer fills 1 - enables the receive slip buffer full interrupt when the transmit slip buffer fills. 1 rxempt_enb r/w 0 receive slip buffer empty interrupt enable this bit enables or disables the receives slip buffer empty interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive slip buffer empty interrupt is declared when the receive slip buffer is emptied. if the receive slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and the interrupt status bit will be set to ?1?. 0 = disables the receive slip buffer empty interrupt when the transmit slip buffer empties 1 - enables the receive slip buffer empty interrupt when the trans - mit slip buffer empties. 0 rxslip_enb r/w 0 receive slip buffer slips interrupt enable this bit enables or disables the receive slip buffer slips interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive slip buffer slips interrupt is declared when either the receive slip buffer is filled or emptied. if the receive slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and the interrupt status bit will be set to ?1?. the interrupt status bit will be set to ?1? in either one of these two conditions: 1. if the receive slip buffer is emptied and a read operation occurs, then a full frame of data will be repeated, and this interrupt bit will be set to ?1?. 2. if the receive slip buffer is full and a write operation occurs, then a full frame of data will be deleted, and this interrupt bit will be set to ?1?. 0 = disables the receive slip buffer slips interrupt when the trans - mit slip buffer empties or fills 1 - enables the receive slip buffer slips interrupt when the trans - mit slip buffer empties or fills. t able 101: s lip b uffer i nterrupt e nable r egister (sbier) h ex a ddress : 0 x nb09 b it f unction t ype d efault d escription -o peration
xrt86vl34 122 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 102: r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) h ex a ddress : 0 x nb0a b it f unction t ype d efault d escription -o peration 7 auxpstat ro 0 auxp state this read only bit indicates whether or not the receive e1 framer block is currently detecting auxiliary (101010....) pattern. 0 = indicates that the receive e1 framer block is not currently detecting the auxiliary (101010....)pattern. 1 = indicates that the receive e1 framer block is currently detect - ing the auxiliary (101010....)pattern. 6 auxpint rur/wc 0 change in auxiliary pattern interrupt status this reset-upon-read bit field indicates whether or not the ?change in auxiliary pattern? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the auxiliary pattern. 2. whenever the receive e1 framer block no longer detects the auxiliary pattern 0 = indicates that the ?change in auxiliary pattern? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in auxiliary pattern? interrupt has occurred since the last read of this register 5 noncrcstat ro 0 crc-4-to-non-crc-4 interworking state this read only bit indicates the status of crc-4 interworking sta - tus when annex b is enabled. (modenb bit in register 0xn107) when annex b is enabled, g.706 annex b crc-4 multiframe align - ment algorithm is implemented. if crc-4 alignment is enabled and not achieved in 400msec while the basic frame alignment signal is present, it is assumed that the remote end is a non crc-4 equip - ment. then, a crc-to-non-crc interworking interrupt status will be generated. 0 = indicates crc-4 to non-crc-4 interworking is not established. 1 = indicates crc-4 to non-crc-4 interworking is established.
xrt86vl34 123 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 4 noncrcint rur/wc 0 change of crc-4-to-non-crc-4 interworking interrupt status - this reset-upon-read bit field indicates whether or not the ?change in crc-4 to non-crc-4 interworking? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the crc-4 to non-crc-4 interworking condition. 2. whenever the receive e1 framer block detects the non- crc-4 to crc-4 interworking condition. 0 = indicates that the ?change in crc-4 to non-crc-4 interworking? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in crc-4 to non-crc-4 interworking? interrupt has occurred since the last read of this register 3-0 for t1 mode only t able 102: r eceive l oopback c ode i nterrupt and s tatus r egister (rlcisr) h ex a ddress : 0 x nb0a b it f unction t ype d efault d escription -o peration
xrt86vl34 124 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 103: r eceive l oopback c ode i nterrupt e nable r egister (rlcier) h ex a ddress : 0 x nb0b b it f unction t ype d efault d escription -o peration 6 auxpintenb r/w 0 change in auxiliary pattern interrupt enable this read write bit field enables or disables the ?change in aux - iliary pattern? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the auxiliary pattern. 2. whenever the receive e1 framer block no longer detects the auxiliary pattern 0 = disables the ?change in auxiliary pattern? interrupt within the e1 receive framer. 1 - enables the ?change in auxiliary pattern? interrupt within the e1 receive framer. 5 reserved - - reserved 4 noncrcenb r/w 0 change of crc-4-to-non-crc-4 interworking interrupt enable this bit enables or disables the ?change in crc-4 to non-crc-4 interworking? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the crc-4 to non-crc-4 interworking condition. 2. whenever the receive e1 framer block detects the non- crc-4 to crc-4 interworking condition. 0 = disables the ?change in crc-4 to non-crc-4 interworking? interrupt within the e1 receive framer. 1 - enables the ?change in crc-4 to non-crc-4 interworking? interrupt within the e1 receive framer. 3-2 reserved - - reserved 1-0 reserved for t1 mode only
xrt86vl34 125 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 104: r eceive sa i nterrupt s tatus r egister (rsaisr) h ex a ddress : 0 x nb0c b it f unction t ype d efault d escription -o peration 7 sa6_1111 rur/ wc 0 change in debounced sa6 = 1111 interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6= 1111? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1111 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1111 pattern. 0 = indicates that the ?change in debounced sa6= 1111? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6= 1111? interrupt has occurred since the last read of this register 6 sa6_1110 rur/ wc 0 change in debounced sa6 = 1110 interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=1110? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1110 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1110 pattern. 0 = indicates that the ?change in debounced sa6=1110? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6=1110? interrupt has occurred since the last read of this register 5 sa6_1100 rur/ wc 0 change in debounced sa6 = 1100 interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=1100? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1100 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1100 pattern. 0 = indicates that the ?change in debounced sa6=1100? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6=1100? interrupt has occurred since the last read of this register
xrt86vl34 126 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 4 sa6_1010 rur/ wc 0 change in debounced sa6 = 1010 interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=1010? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1010 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1010 pattern. 0 = indicates that the ?change in debounced sa6=1010? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6=1010? interrupt has occurred since the last read of this register 3 sa6_1000 rur/ wc 0 change in debounced sa6 = 1000 interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=1000? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1000 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1000 pattern. 0 = indicates that the ?change in debounced sa6=1000? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6=1000? interrupt has occurred since the last read of this register 2 sa6_001x rur/ wc 0 change in debounced sa6 = 001x interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=001x? interrupt has occurred since the last read of this register, where x is don?t care. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 001x pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 001x pattern. 0 = indicates that the ?change in debounced sa6=001x? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6=001x? interrupt has occurred since the last read of this register t able 104: r eceive sa i nterrupt s tatus r egister (rsaisr) h ex a ddress : 0 x nb0c b it f unction t ype d efault d escription -o peration
xrt86vl34 127 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 1 sa6_other rur/ wc 0 debounced sa6 = other combination interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=other combination? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt when it detects the debounced sa 6 equals to any other combinations. 0 = indicates that the ?debounced sa6 = other combination? inter - rupt has not occurred since the last read of this register 1 = indicates that the ?debounced sa6 = other combination? inter - rupt has occurred since the last read of this register 0 sa6_0000 rur/ wc 0 change in debounced sa6 = 0000 interrupt status this reset-upon-read bit field indicates whether or not the ?change in debounced sa6=0000? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 0000 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 0000 pattern. 0 = indicates that the ?change in debounced sa6=0000? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in debounced sa6=0000? interrupt has occurred since the last read of this register t able 104: r eceive sa i nterrupt s tatus r egister (rsaisr) h ex a ddress : 0 x nb0c b it f unction t ype d efault d escription -o peration
xrt86vl34 128 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 105: r eceive sa i nterrupt e nable r egister (rsaier) h ex a ddress : 0 x nb0d b it f unction t ype d efault d escription -o peration 7 sa6_1111_enb r/w 0 change in debounced sa6 = 1111 interrupt enable this bit enables or disables the ?change in debounced sa6=1111? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1111 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1111 pattern. 0 = disables the ?change in debounced sa6= 1111? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6= 1111? interrupt within the receive e1 framer block 6 sa6_1110_enb r/w 0 change in debounced sa6 = 1110 interrupt enable this bit enables or disables the ?change in debounced sa6=1110? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1110 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1110 pattern. 0 = disables the ?change in debounced sa6=1110? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6=1110? interrupt within the receive e1 framer block 5 sa6_1100_enb r/w 0 change in debounced sa6 = 1100 interrupt enable this bit enables or disables the ?change in debounced sa6=1100? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1100 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1100 pattern. 0 = disables the ?change in debounced sa6=1100? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6=1100? interrupt within the receive e1 framer block
xrt86vl34 129 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 4 sa6_1010_enb r/w 0 change in debounced sa6 = 1010 interrupt enable this bit enables or disables the ?change in debounced sa6=1010? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1010 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1010 pattern. 0 = disables the ?change in debounced sa6=1010? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6=1010? interrupt within the receive e1 framer block 3 sa6_1000_enb r/w 0 change in debounced sa6 = 1000 interrupt enable this bit enables or disables the ?change in debounced sa6=1000? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 1000 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 1000 pattern. 0 = disables the ?change in debounced sa6=1000? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6=1000? interrupt within the receive e1 framer block 2 sa6_001x_enb r/w 0 change in debounced sa6 = 001x interrupt enable this bit enables or disables the ?change in debounced sa6=001x? interrupt within the e1 receive framer, where x is don?t care. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 001x pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 001x pattern. 0 = disables the ?change in debounced sa6=001x? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6=001x? interrupt within the receive e1 framer block t able 105: r eceive sa i nterrupt e nable r egister (rsaier) h ex a ddress : 0 x nb0d b it f unction t ype d efault d escription -o peration
xrt86vl34 130 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 sa6_other_enb r/w 0 debounced sa6 = other combination interrupt enable this bit enables or disables the ?debounced sa6=other combina - tion? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt when it detects the debounced sa6 equals to any other combination. 0 = disables the ?debounced sa6=other combination? interrupt within the receive e1 framer block 1 - enables the ?debounced sa6=other combination? interrupt within the receive e1 framer block 0 sa6_0000_enb r/w 0 change in debounced sa6 = 0000 interrupt enable this bit enables or disables the ?change in debounced sa6=0000? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the debounced sa6 equals to the 0000 pattern. 2. whenever the receive e1 framer block no longer detects the debounced sa6 equals to the 0000 pattern. 0 = disables the ?change in debounced sa6=0000? interrupt within the receive e1 framer block 1 - enables the ?change in debounced sa6=0000? interrupt within the receive e1 framer block t able 105: r eceive sa i nterrupt e nable r egister (rsaier) h ex a ddress : 0 x nb0d b it f unction t ype d efault d escription -o peration
xrt86vl34 131 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 106: e xcessive z ero s tatus r egister (exzsr) h ex a ddress : 0 x nb0e b it f unction t ype d efault d escription -o peration 5 sa7_eq_0_stat ro 0 received sa7 equals ?0? state this read only bit field indicates whether or not the receive e1 framer is currently declaring the ?sa7 equals 0? status within the incoming e1 national bits. the ?received sa7 equals 0? status will be set to ?1? if the received sa7 is 0 for at least 2 out of 3 times. 0 = indicates the e1 receive framer is currently not declaring the ?received sa7 equals 0? status. 1 = indicates the e1 receive framer is currently declaring the ?received sa7 equals 0? status. 4-2 reserved - - reserved 1 sa7_eq_0_int rur/ wc 0 change in ?sa 7 equals 0? interrupt status this reset-upon-read bit field indicates whether or not the ?change in sa7 equals 0? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the received sa7 equals to 0 for at least 2 out of 3 times. 2. whenever the receive e1 framer block no longer detects the received sa7 equals to the 0. 0 = indicates that the ?change in sa7 equals 0? interrupt has not occurred since the last read of this register 1 = indicates that the ?change in sa7 equals 0? interrupt has occurred since the last read of this register 0 exz_status rur/ wc 0 change in excessive zero condition interrupt status this reset-upon-read bit field indicates whether or not the ?change in excessive zero condition? interrupt within the e1 receive framer block has occurred since the last read of this regis - ter. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the excessive zero condition. 2. whenever the receive e1 framer block clears the excessive zero condition 0 = indicates the ?change in excessive zero condition? interrupt has not occurred since the last read of this register 1 = indicates the ?change in excessive zero condition? interrupt has occurred since the last read of this register
xrt86vl34 132 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 107: e xcessive z ero e nable r egister (exzer) h ex a ddress : 0 x nb0f b it f unction t ype d efault d escription -o peration 1 sa7_eq_0_enb r/w 0 change in ?sa 7 equals 0? interrupt enable this bit enables or disables the ?change in sa7 equals 0? interrupt within the receive e1 framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the received sa7 equals to 0 for at least 2 out of 3 times. 2. whenever the receive e1 framer block no longer detects the received sa7 equals to the 0. 0 = disables the ?change in sa7 equals 0? interrupt within the e1 receive framer block. 1 = enables the ?change in sa7 equals 0? interrupt within the e1 receive framer block. 0 exz_enb r/w 0 change in excessive zero condition interrupt enable this bit enables or disables the ?change in excessive zero condi - tion? interrupt within the e1 receive framer. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block detects the excessive zero condition. 2. whenever the receive e1 framer block clears the excessive zero condition 0 = disables the ?change in excessive zero condition? interrupt within the receive e1 framer block 1 - enables the ?change in excessive zero condition? interrupt within the receive e1 framer block
xrt86vl34 133 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 108: r x los/crc i nterrupt s tatus r egister (rlcisr) h ex a ddress : 0 xn b12 b it f unction t ype d efault d escription -o peration 4 ais16 ro 0 ais 16 state this bit indicates whether or not the receive e1 framer is declaring ais 16 (time slot 16 = all ones signal) alarm condition. 0 - indicates the receive e1 framer is currently not declaring the ais16 alarm condition. 1 - indicates the receive e1 framer is currently declaring the ais16 alarm condition. 3 rxlosint rur/ wc 0 change in receive los condition interrupt status this bit indicates whether or not the ?change in receive los condi - tion? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares the receive los condition. 2. whenever the receive e1 framer block clears the receive los condition. 0 = indicates that the ?change in receive los condition? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in receive los condition? interrupt has occurred since the last read of this register. 2 crclock_int rur/ wc 0 change in crc multiframe alignment in-frame interrupt status this bit indicates whether or not the e1 receive framer block has lost or gained crc multiframe alignment since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares crc multiframe alignment lock. 2. whenever the receive e1 framer block declares loss of crc multiframe alignment. 0 = indicates that the ?change in crc multiframe alignment in- frame? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in crc multiframe alignment in- frame? interrupt has occurred since the last read of this register.
xrt86vl34 134 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 caslock_int rur/ wc 0 change in cas multiframe alignment in-frame interrupt status this bit indicates whether or not the e1 receive framer block has lost or gained cas multiframe alignments since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares cas multiframe alignment lock. 2. whenever the receive e1 framer block declares loss of cas multiframe alignment. 0 = indicates that the ?change in cas multiframe alignment in- frame? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in cas multiframe alignment in- frame? interrupt has occurred since the last read of this register. 0 ais16_int rur/ wc 0 change in ais16 alarm condition interrupt status this bit indicates whether or not the ?change in ais16 alarm condi - tion? interrupt has occurred since the last read of this register. if this interrupt is enabled, then the receive e1 framer block will generate an interrupt in response to either one of the following conditions. 1. whenever the receive e1 framer block declares ais16 (timeslot 16 = all ones) condition. 2. whenever the receive e1 framer block clears ais16 (timeslot 16 = all ones) condition. 0 = indicates that the ?change in ais16 condition? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in ais16 condition? interrupt has occurred since the last read of this register. t able 108: r x los/crc i nterrupt s tatus r egister (rlcisr) h ex a ddress : 0 xn b12 b it f unction t ype d efault d escription -o peration
xrt86vl34 135 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 109: r x los/crc i nterrupt e nable r egister (rlcier) h ex a ddress : 0 xn b13 b it f unction t ype d efault d escription -o peration 3 rxlos_enb r/w 0 change in receive los condition interrupt enable this bit enables the ?change in receive los condition? interrupt. 0 = enables ?change in receive los condition? interrupt. 1 = disables ?change in receive los condition? interrupt. 2 crclock_enb r/w 0 change in crc multiframe alignment in-frame interrupt enable this bit enables the ?change in crc multiframe alignment in-frame? interrupt. 0 = enables ?change in crc multiframe alignment in-frame? interrupt. 1 = disables ?change in crc multiframe alignment in-frame? interrupt. 1 caslock_enb r/w 0 change in cas multiframe alignment in-frame interrupt enable this bit enables the ?change in cas multiframe alignment in-frame? interrupt. 0 = enables ?change in cas multiframe alignment in-frame? interrupt. 1 = disables ?change in cas multiframe alignment in-frame? interrupt. 0 ais16_enb r/w 0 change in ais16 condition interrupt enable this bit enables the ?change in ais16 (time slot 16 = all ones) condi - tion? interrupt. 0 = enables ?change in ais 16 condition? interrupt. 1 = disables ?change in ais 16 condition? interrupt.
xrt86vl34 136 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 110: d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x nb16 b it f unction t ype d efault d escription -o peration 7 msg type ro 0 hdlc2 message type identifier this read only bit indicates the type of data link message received by receive hdlc 2 controller. two types of data link mes - sages are supported within the xrt86vl34 device: message ori - ented signaling (mos) or bit-oriented signalling (bos). 0 = indicates bit-oriented signaling (bos) type data link message is received 1 = indicates message oriented signaling (mos) type data link message is received 6 txsot rur/ wc 0 transmit hdlc2 controller start of transmission (txsot) interrupt status this reset-upon-read bit indicates whether or not the ?transmit hdlc2 controller start of transmission (txsot) ?interrupt has occurred since the last read of this register. transmit hdlc2 con - troller will declare this interrupt when it has started to transmit a data link message. for sending large hdlc messages, start loading the next available buffer once this interrupt is detected. 0 = transmit hdlc2 controller start of transmission (txsot) inter - rupt has not occurred since the last read of this register 1 = transmit hdlc2 controller start of transmission interrupt (txsot) has occurred since the last read of this register. 5 rxsot rur/ wc 0 receive hdlc2 controller start of reception (rxsot) interrupt status this reset-upon-read bit indicates whether or not the receive hdlc2 controller start of reception (rxsot) interrupt has occurred since the last read of this register. receive hdlc2 con - troller will declare this interrupt when it has started to receive a data link message. 0 = receive hdlc2 controller start of reception (rxsot) interrupt has not occurred since the last read of this register 1 = receive hdlc2 controller start of reception (rxsot) interrupt has occurred since the last read of this register 4 txeot rur/ wc 0 transmit hdlc2 controller end of transmission (txeot) inter - rupt status this reset-upon-read bit indicates whether or not the transmit hdlc2 controller end of transmission (txeot) interrupt has occurred since the last read of this register. transmit hdlc2 con - troller will declare this interrupt when it has completed its transmis - sion of a data link message. for sending large hdlc messages, it is critical to load the next available buffer before this interrupt occurs. 0 = transmit hdlc2 controller end of transmission (txeot) inter - rupt has not occurred since the last read of this register 1 = transmit hdlc2 controller end of transmission (txeot) inter - rupt has occurred since the last read of this register
xrt86vl34 137 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 3 rxeot rur/ wc 0 receive hdlc2 controller end of reception (rxeot) interrupt status this reset-upon-read bit indicates whether or not the receive hdlc2 controller end of reception (rxeot) interrupt has occurred since the last read of this register. receive hdlc2 controller will declare this interrupt once it has completely received a full data link message, or once the buffer is full. 0 = receive hdlc2 controller end of reception (rxeot) interrupt has not occurred since the last read of this register 1 = receive hdlc2 controller end of reception (rxeot) interrupt has occurred since the last read of this register 2 fcs error rur/ wc 0 fcs error interrupt status this reset-upon-read bit indicates whether or not the fcs error interrupt has occurred since the last read of this register. receive hdlc2 controller will declare this interrupt when it has detected the fcs error in the most recently received data link message. 0 = fcs error interrupt has not occurred since the last read of this register 1 = fcs error interrupt has occurred since the last read of this regis - ter 1 rx abort rur/ wc 0 receipt of abort sequence interrupt status this reset-upon-read bit indicates whether or not the receipt of abort sequence interrupt has occurred since last read of this regis - ter. receive hdlc2 controller will declare this interrupt if it detects the abort sequence (i.e. a string of seven (7) consecutive 1?s) in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occurred since last read of this register 1 = receipt of abort sequence interrupt has occurred since last read of this register 0 rxidle rur/ wc 0 receipt of idle sequence interrupt status this reset-upon-read bit indicates whether or not the receipt of idle sequence interrupt has occurred since the last read of this reg - ister. the receive hdlc2 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. if rxidle "and" rxeot occur together, then the entire hdlc message has been received. 0 = receipt of idle sequence interrupt has not occurred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 110: d ata l ink s tatus r egister 2 (dlsr2) h ex a ddress : 0 x nb16 b it f unction t ype d efault d escription -o peration
xrt86vl34 138 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 111: d ata l ink i nterrupt e nable r egister 2 (dlier2) h ex a ddress : 0 x nb17 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc2 controller start of transmission (txsot) interrupt enable this bit enables or disables the ?transmit hdlc2 controller start of transmission (txsot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit hdlc2 controller will generate an interrupt when it has started to transmit a data link message. 0 = disables the transmit hdlc2 controller start of transmission (txsot) interrupt. 1 = enables the transmit hdlc2 controller start of transmission (txsot) interrupt. 5 rxsot enb r/w 0 receive hdlc2 controller start of reception (rxsot) interrupt enable this bit enables or disables the ?receive hdlc2 controller start of reception (rxsot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc2 controller will generate an interrupt when it has started to receive a data link message. 0 = disables the receive hdlc2 controller start of reception (rxsot) interrupt. 1 = enables the receive hdlc2 controller start of reception (rxsot) interrupt. 4 txeot enb r/w 0 transmit hdlc2 controller end of transmission (txeot) inter - rupt enable this bit enables or disables the ?transmit hdlc2 controller end of transmission (txeot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit hdlc2 controller will generate an interrupt when it has finished transmitting a data link message. 0 = disables the transmit hdlc2 controller end of transmission (txeot) interrupt. 1 = enables the transmit hdlc2 controller end of transmission (txeot) interrupt. 3 rxeot enb r/w 0 receive hdlc2 controller end of reception (rxeot) interrupt enable this bit enables or disables the ?receive hdlc2 controller end of reception (rxeot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc2 controller will generate an interrupt when it has finished receiving a complete data link message. 0 = disables the receive hdlc2 controller end of reception (rxeot) interrupt. 1 = enables the receive hdlc2 controller end of reception (rxeot) interrupt.
xrt86vl34 139 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 fcs err enb r/w 0 fcs error interrupt enable this bit enables or disables the ?received fcs error ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc2 controller will generate an interrupt when it has detected the fcs error within the incoming data link message. 0 = disables the ?receive fcs error? interrupt. 1 = enables the ?receive fcs error? interrupt. 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable this bit enables or disables the ?receipt of abort sequence? inter - rupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc2 controller will generate an interrupt when it has detected the abort sequence (i.e. a string of seven (7) consecutive 1?s) within the incoming data link channel. 0 = disables the ?receipt of abort sequence? interrupt. 1 = enables the ?receipt of abort sequence? interrupt. 0 rxidle enb r/w 0 receipt of idle sequence interrupt enable this bit enables or disables the ?receipt of idle sequence? interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc2 controller will generate an interrupt when it has detected the idle sequence octet (i.e. 0x7e) within the incoming data link channel. 0 = disables the ?receipt of idle sequence? interrupt. 1 = enables the ?receipt of idle sequence? interrupt. t able 111: d ata l ink i nterrupt e nable r egister 2 (dlier2) h ex a ddress : 0 x nb17 b it f unction t ype d efault d escription -o peration
xrt86vl34 140 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 112: d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 xn b26 b it f unction t ype d efault d escription -o peration 7 msg type rur/ wc 0 hdlc3 message type identifier this read only bit indicates the type of data link message received by receive hdlc 3 controller. two types of data link messages are supported within the xrt86vl34 device: message oriented signaling (mos) or bit-oriented signalling (bos). 0 = indicates bit-oriented signaling (bos) type data link message is received 1 = indicates message oriented signaling (mos) type data link mes - sage is received 6 txsot rur/ wc 0 transmit hdlc3 controller start of transmission (txsot) inter - rupt status this reset-upon-read bit indicates whether or not the ?transmit hdlc3 controller start of transmission (txsot) ?interrupt has occurred since the last read of this register. transmit hdlc3 controller will declare this interrupt when it has started to transmit a data link mes - sage. for sending large hdlc messages, start loading the next avail - able buffer once this interrupt is detected. 0 = transmit hdlc3 controller start of transmission (txsot) interrupt has not occurred since the last read of this register 1 = transmit hdlc3 controller start of transmission interrupt (txsot) has occurred since the last read of this register. 5 rxsot rur/ wc 0 receive hdlc3 controller start of reception (rxsot) interrupt status this reset-upon-read bit indicates whether or not the receive hdlc3 controller start of reception (rxsot) interrupt has occurred since the last read of this register. receive hdlc3 controller will declare this interrupt when it has started to receive a data link mes - sage. 0 = receive hdlc3 controller start of reception (rxsot) interrupt has not occurred since the last read of this register 1 = receive hdlc3 controller start of reception (rxsot) interrupt has occurred since the last read of this register 4 txeot rur/ wc 0 transmit hdlc3 controller end of transmission (txeot) interrupt status this reset-upon-read bit indicates whether or not the transmit hdlc3 controller end of transmission (txeot) interrupt has occurred since the last read of this register. transmit hdlc3 controller will declare this interrupt when it has completed its transmission of a data link message. for sending large hdlc messages, it is critical to load the next available buffer before this interrupt occurs. 0 = transmit hdlc3 controller end of transmission (txeot) interrupt has not occurred since the last read of this register 1 = transmit hdlc3 controller end of transmission (txeot) interrupt has occurred since the last read of this register
xrt86vl34 141 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 3 rxeot rur/ wc 0 receive hdlc3 controller end of reception (rxeot) interrupt status this reset-upon-read bit indicates whether or not the receive hdlc3 controller end of reception (rxeot) interrupt has occurred since the last read of this register. receive hdlc3 controller will declare this interrupt once it has completely received a full data link message, or once the buffer is full. 0 = receive hdlc3 controller end of reception (rxeot) interrupt has not occurred since the last read of this register 1 = receive hdlc3 controller end of reception (rxeot) interrupt has occurred since the last read of this register 2 fcs error rur/ wc 0 fcs error interrupt status this reset-upon-read bit indicates whether or not the fcs error inter - rupt has occurred since the last read of this register. receive hdlc3 controller will declare this interrupt when it has detected the fcs error in the most recently received data link message. 0 = fcs error interrupt has not occurred since the last read of this reg - ister 1 = fcs error interrupt has occurred since the last read of this register 1 rx abort rur/ wc 0 receipt of abort sequence interrupt status this reset-upon-read bit indicates whether or not the receipt of abort sequence interrupt has occurred since last read of this register. receive hdlc3 controller will declare this interrupt if it detects the abort sequence (i.e. a string of seven (7) consecutive 1?s) in the incoming data link channel. 0 = receipt of abort sequence interrupt has not occurred since last read of this register 1 = receipt of abort sequence interrupt has occurred since last read of this register 0 rxidle rur/ wc 0 receipt of idle sequence interrupt status this reset-upon-read bit indicates whether or not the receipt of idle sequence interrupt has occurred since the last read of this register. the receive hdlc3 controller will declare this interrupt if it detects the flag sequence octet (0x7e) in the incoming data link channel. if rxi - dle "and" rxeot occur together, then the entire hdlc message has been received. 0 = receipt of idle sequence interrupt has not occurred since last read of this register 1 = receipt of idle sequence interrupt has occurred since last read of this register. t able 112: d ata l ink s tatus r egister 3 (dlsr3) h ex a ddress : 0 xn b26 b it f unction t ype d efault d escription -o peration
xrt86vl34 142 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 113: d ata l ink i nterrupt e nable r egister 3 (dlier3) h ex a ddress : 0 x nb27 b it f unction t ype d efault d escription -o peration 7 reserved - - reserved 6 txsot enb r/w 0 transmit hdlc3 controller start of transmission (txsot) interrupt enable this bit enables or disables the ?transmit hdlc3 controller start of transmission (txsot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit hdlc3 controller will generate an interrupt when it has started to transmit a data link message. 0 = disables the transmit hdlc3 controller start of transmission (txsot) interrupt. 1 = enables the transmit hdlc3 controller start of transmission (txsot) interrupt. 5 rxsot enb r/w 0 receive hdlc3 controller start of reception (rxsot) interrupt enable this bit enables or disables the ?receive hdlc3 controller start of reception (rxsot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc3 controller will generate an interrupt when it has started to receive a data link message. 0 = disables the receive hdlc3 controller start of reception (rxsot) interrupt. 1 = enables the receive hdlc3 controller start of reception (rxsot) interrupt. 4 txeot enb r/w 0 transmit hdlc3 controller end of transmission (txeot) inter - rupt enable this bit enables or disables the ?transmit hdlc3 controller end of transmission (txeot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the transmit hdlc3 controller will generate an interrupt when it has finished transmitting a data link message. 0 = disables the transmit hdlc3 controller end of transmission (txeot) interrupt. 1 = enables the transmit hdlc3 controller end of transmission (txeot) interrupt. 3 rxeot enb r/w 0 receive hdlc3 controller end of reception (rxeot) interrupt enable this bit enables or disables the ?receive hdlc3 controller end of reception (rxeot) ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc3 controller will generate an interrupt when it has finished receiving a complete data link message. 0 = disables the receive hdlc3 controller end of reception (rxeot) interrupt. 1 = enables the receive hdlc3 controller end of reception (rxeot) interrupt.
xrt86vl34 143 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 2 fcs err enb r/w 0 fcs error interrupt enable this bit enables or disables the ?received fcs error ?interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc3 controller will generate an interrupt when it has detected the fcs error within the incoming data link message. 0 = disables the ?receive fcs error? interrupt. 1 = enables the ?receive fcs error? interrupt. 1 rxabort enb r/w 0 receipt of abort sequence interrupt enable this bit enables or disables the ?receipt of abort sequence? inter - rupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc3 controller will generate an interrupt when it has detected the abort sequence (i.e. a string of seven (7) consecutive 1?s) within the incoming data link channel. 0 = disables the ?receipt of abort sequence? interrupt. 1 = enables the ?receipt of abort sequence? interrupt. 0 rxidle enb r/w 0 receipt of idle sequence interrupt enable this bit enables or disables the ?receipt of idle sequence? interrupt within the xrt86vl34 device. once this interrupt is enabled, the receive hdlc3 controller will generate an interrupt when it has detected the idle sequence octet (i.e. 0x7e) within the incoming data link channel. 0 = disables the ?receipt of idle sequence? interrupt. 1 = enables the ?receipt of idle sequence? interrupt. t able 113: d ata l ink i nterrupt e nable r egister 3 (dlier3) h ex a ddress : 0 x nb27 b it f unction t ype d efault d escription -o peration
xrt86vl34 144 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 2.0 line interface unit (liu section) registers t able 114: liu c hannel c ontrol r egister 0 (liuccr0) h ex a ddress : 0 x 0f n 0 b it f unction t ype d efault d escription -o peration 7 qrss_n/ prbs_n r/w 0 qrss/prbs select bits these bits are used to select between qrss and prbs. 0 = prbs_n (2 15 - 1) 1 = qrss_n (2 20 - 1) 6 prbs_rx_n/ prbs_ tx _n r/w 0 prbs receive/transmit select: this bit is used to select where the output of the prbs generator is directed if prbs generation is enabled. 0 = normal operation - prbs generator is output on ttip and tring if prbs generation is enabled. 1 = prbs generator is output on rpos and rclk. 5 rxon_n r/w 0 receiver on: this bit permits the user to either turn on or turn off the receive sec - tion of xrt86vl34. if the user turns on the receive section, then xrt86vl34 will begin to receive the incoming data-stream via the rtip and rring input pins. conversely, if the user turns off the receive section, then the entire receive section except the mclkin phase locked loop (pll) will be powered down. 0 = shuts off the receive section of xrt86vl34. 1 = turns on the receive section of xrt86vl34. pbrs generator tx ttip trin g + - bit 6 = "0" pbrs generator rx rpos rne g + - bit 6 = "1"
xrt86vl34 145 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 4-0 eqc[4:0] r/w 00000 equalizer control [4:0]: these bits are used to control the transmit pulse shaping, transmit line build-out (lbo) and receive sensitivity level. the transmit pulse shape can be controlled by adjusting the trans - mit line build-out settings for different cable length in e1 mode. transmit pulse shape can also be controlled by using the arbitrary mode, where users can specify the amplitude of the pulse shape by using the 8 arbitrary pulse segments provided in the liu registers (0x0fn8-0xnfnf), where n is the channel number. the xrt86vl34 device supports both long haul and short haul applications which can also be selected using the eqc[4:0] bits. tab l e 115 presents the corresponding transmit line build out and receive sensitivity settings using different combinations of these five eqc[4:0] bits. t able 114: liu c hannel c ontrol r egister 0 (liuccr0) h ex a ddress : 0 x 0f n 0 b it f unction t ype d efault d escription -o peration
xrt86vl34 146 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 115: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1 m ode /r eceive s ensitivity t ransmit lbo c able 0x00h t1 long haul/36db 0db 100 tp 0x01h t1 long haul/36db -7.5db 100 tp 0x02h t1 long haul/36db -15db 100 tp 0x03h t1 long haul/36db -22.5db 100 tp 0x04h t1 long haul/45db 0db 100 tp 0x05h t1 long haul/45db -7.5db 100 tp 0x06h t1 long haul/45db -15db 100 tp 0x07h t1 long haul/45db -22.5db 100 tp 0x08h t1 short haul/15db 0 to 133 feet (0.6db) 100 tp 0x09h t1 short haul/15db 133 to 266 feet (1.2db) 100 tp 0x0ah t1 short haul/15db 266 to 399 feet (1.8db) 100 tp 0x0bh t1 short haul/15db 399 to 533 feet (2.4db) 100 tp 0x0ch t1 short haul/15db 533 to 655 feet (3.0db) 100 tp 0x0dh t1 short haul/15db arbitrary pulse 100 tp 0x0eh t1 gain mode/29db 0 to 133 feet (0.6db) 100 tp 0x0fh t1 gain mode/29db 133 to 266 feet (1.2db) 100 tp 0x10h t1 gain mode/29db 266 to 399 feet (1.8db) 100 tp 0x11h t1 gain mode/29db 399 to 533 feet (2.4db) 100 tp 0x12h t1 gain mode/29db 533 to 655 feet (3.0db) 100 tp 0x13h t1 gain mode/29db arbitrary pulse 100 tp 0x14h t1 gain mode/29db 0db 100 tp 0x15h t1 gain mode/29db -7.5db 100 tp 0x16h t1 gain mode/29db -15db 100 tp 0x17h t1 gain mode/29db -22.5db 100 tp 0x18h e1 long haul/36db itu g.703 75 coax 0x19h e1 long haul/36db itu g.703 120 tp 0x1ah e1 long haul/45db itu g.703 75 coax 0x1bh e1 long haul/45db itu g.703 120 tp 0x1ch e1 short haul/15db itu g.703 75 coax 0x1dh e1 short haul/15db itu g.703 120 tp 0x1eh e1 gain mode/29db itu g.703 75 coax 0x1fh e1 gain mode/29db itu g.703 120 tp
xrt86vl34 147 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 116: liu c hannel c ontrol r egister 1 (liuccr1) h ex a ddress : 0 x 0f n 1 b it f unction t ype d efault d escription -o peration 7 rxtsel_n r/w 0 receiver termination select: upon power up, the receivers are in ?high? impedance. the liu pro - vides an option for user to have either software or hardware control over receive termination. if rxtcntl (bit 6 in register 0x0fe2) is set to?0?, receive termination can be selected by programming this register bit. to switch control to the hardware pin (rxtsel pin), rxtcntl must be programmed to ?1?. once control has been granted to the hardware pin, rxtsel must be pulled ?high? to switch to internal termination. if rxtcntl is set to?0?, receive termination can be selected by set - ting this bit according to the following table: 6 txtsel_n r/w 0 transmit termination select: this bit is used to select between internal termination or ?high? impedance modes for the e1 transmitter according to the following table: 5-4 tersel[1:0] r/w 00 termination impedance select [1:0]: these bits are used to control the transmit and receive termination impedance when the liu block is configured in internal termination mode. in internal termination mode, (i.e., txtsel = ?1? and rxtsel = ?1?), internal transmit and receive termination can be selected according to the following table: n ote : in the internal termination mode, the transmitter output should be ac coupled to the transformer. rxtsel rx termination 0 1 "high" impedance internal txtsel tx termination 0 1 "high" impedance internal tersel1 tersel0 0 0 0 1 1 0 1 1 internal transmit and receive termination 100 110 75 120
xrt86vl34 148 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 rxjasel_n r/w 0 receive jitter attenuator enable this bit permits the user to enable or disable the jitter attenuator in the receive path within the xrt86vl34 device. 0 = disables the jitter attenuator to operate in the receive path within the receive e1 liu block. 1 = enables the jitter attenuator to operate in the receive path within the receive e1 liu block. 2 txjasel_n r/w 0 transmit jitter attenuator enable this bit permits the user to enable or disable the jitter attenuator in the transmit path within the xrt86vl34 device. 0 = disables the jitter attenuator to operate in the transmit path within the transmit e1 liu block. 1 = enables the jitter attenuator to operate in the transmit path within the transmit e1 liu block. 1 jabw_n r/w 0 jitter attenuator bandwidth select: in e1 mode, this bit is used to select the jitter attenuator bandwidth as well as the fifo size. 1 = selects a 1.5hz bandwidth for the jitter attenuator. the fifo length will be automatically set to 64 bits. 0 = setting this bit to ?0? will select 10hz bandwidth for the jitter attenuator. the fifos (bit d0 of this register) will be used to select the fifo size. the table below presents the jitter attenuator and fifo settings corresponding to the combinations of this jabw and fifos bits in both t1 and e1 mode . 0 fifos_n r/w 0 fifo size select: see table of bit d1 above for the function of this bit. t able 116: liu c hannel c ontrol r egister 1 (liuccr1) h ex a ddress : 0 x 0f n 1 b it f unction t ype d efault d escription -o peration 0 1 0 1 0 1 0 1 fifos_n bit d0 0 0 1 1 0 0 1 1 jabw bit d1 t1 t1 t1 t1 e1 e1 e1 e1 mode 32 64 32 64 32 64 64 64 fifo size 3 3 3 3 10 10 1.5 1.5 ja b-w hz
xrt86vl34 149 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 117: liu c hannel c ontrol r egister 2 (liuccr2) h ex a ddress : 0 x 0f n 2 b it f unction t ype d efault d escription -o peration 7 invqrss_n r/w 0 invert qrss pattern: this bit inverts the output prbs/qrss pattern if the liu block is configured to transmit a prbs/qrss pattern. 0 = the liu will not invert the output prbs/qrss pattern 1 = the liu will invert the output prbs/qrss pattern 6-4 txtest[2:0] r/w 000 transmit test pattern [2:0] : these bits are used to configure the transmit e1 liu block to gen - erate and transmit test patterns according to the following table. use of these bits automatically places the liu section in single rail mode. when this happens, the framer section must be placed in single rail mode in reg 0xn101. tdqrss (transmit/detect quasi-random signal): qrss pattern is a 2 15 -1 pseudo-random bit sequence (prbs) pat - tern. taos (transmit all ones): whenever the user implements this configuration setting, the trans - mit e1 liu block will ignore the data that it is accepting from the transmit e1 framer block (as well as the upstream system-side ter - minal equipment) and overwrite this data with the all ones pattern. tluc (transmit network loop-up code): the transmit e1 liu block will generate and transmit the network loop-up code of ?00001? to the line for the selected channel num - ber n. when network loop-up code is being transmitted, the xrt86vl34 will ignore the ?automatic loop-code detection and remote loop- back activation? (nlcde1 =?1?, nlcde0 =?1? of register 0x0fn3) in order to avoid activating remote digital loop-back automatically when the remote terminal responds to the loop-back request. tldc (transmit network loop-down code): the transmit e1 liu block will generate and transmit the network loop-down code of ?001? to the line for the selected channel num - ber n. 0 0 0 1 1 0 1 1 1 1 1 1 x x 0 no pattern tdqrss taos tluc test pattern tldc txtest1 txtest0 txtest2
xrt86vl34 150 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 txon_n r/w 0 transmitter on: this bit permits the user to either turn on or turn off the transmit driver of xrt86vl34. if the user turns on the transmit driver, then xrt86vl34 will begin to transmit ds1 data (on the line) via the ttip and tring output pins. conversely, if the user turns off the transmit driver, then the ttip and tring output pins will be tri-stated. 0 = shuts off the transmit driver associated with the xrt86vl34 device and tri-states the ttip and tring output pins. 1 = turns on the transmit driver associated with the xrt86vl34 device. n ote : if the user wishes to exercise software control over the state of the transmit driver of the xrt86vl34, then it is imperative that the user pull the txon pin to a logic ?high? level. 2-0 loop2_n r/w 000 loop-back control [2:0]: these bits control the loop-back modes of the liu section, accord - ing to the table below. t able 117: liu c hannel c ontrol r egister 2 (liuccr2) h ex a ddress : 0 x 0f n 2 b it f unction t ype d efault d escription -o peration loop2 0 1 1 1 1 loop1 x 0 0 1 1 loop0 x 0 1 0 1 loop-back mode no loop-back dual loop-back analog loop-back remote loop-back digital loop-back
xrt86vl34 151 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 118: liu c hannel c ontrol r egister 3 (liuccr3) h ex a ddress : 0 x 0f n 3 b it f unction t ype d efault d escription -o peration 7-6 nlcde[1:0] r/w 00 network loop code detection enable [1:0]: these bits are used to control the loop-code detection on the receive path of each channel, according to the table below. this part must be in single rail mode to detect . loop-up code detection enable: the xrt86vl34 is configured to monitor the receive data for the loop-up code pattern (i.e. a string of four ?0?s followed by one ?1? pattern). when the presence of the ?00001? pattern is detected for more than 5 seconds, the status of the nlcd bit (bit 3 of register 0x0fn5) is set to ?1? and if the nlcd interrupt is enabled (bit 3 of register 0x0fn4), an interrupt will be generated. loop-down code detection enable: the xrt86vl34 is configured to monitor the receive data for the loop-down code pattern (i.e. a string of two ?0?s followed by one ?1? pattern). when the presence of the ?001? pattern is detected for more than 5 seconds, the status of the nlcd bit (bit 3 of register 0x0fn5) is set to ?1? and if the nlcd interrupt is enabled (bit 3 of register 0x0fn4), an interrupt will be generated. automatic loop-up code detection and remote loop back activation enable: when this mode is enabled, the state of the nlcd bit (bit 3 of regis - ter 0x0fn5) is reset to ?0? and the xrt86vl34 is configured to mon - itor the receive data for the loop-up code. if the ?00001? pattern is detected for longer than 5 seconds, then the nlcd bit (bit 3 of regis - ter 0x0fn5) is set ?1?, and remote loop-back is activated. once the remote loop-back is activated, the xrt86vl34 is automatically pro - grammed to monitor the receive data for the loop-down code. the nlcd bit stays set even after the chip stops receiving the loop-up code. the remote loop-back condition is removed only when the xrt86vl34 receives the loop-down code for more than 5 seconds or if the automatic loop-code detection mode is terminated. 5-2 reserved r/w 0 this bit is not used nlcde[1:0] n etwork l oop c ode d etection e nable 00 disables loop code detection 01 enables loop-up code detection on the receive path. 10 enables loop-down code detection on the receive path. 11 enables automatic loop-up code detection on the receive path and remote loop-back activation upon detecting loop-up code.
xrt86vl34 152 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 insber_n r/w 0 insert bit error: this bit is used to insert a single bit error on the transmitter of the e1 liu block. when the e1 liu block is configured to transmit and detect the qrss pattern, (i.e., txtest[2:0] bits set to ?b100?), a ?0? to ?1? tran - sition of this bit will insert a bit error in the transmitted qrss pattern of the selected channel number n. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of bit error, a ?0? should be written in this bit location before writing a ?1?. 0 reserved r/w 0 this bit is not used t able 118: liu c hannel c ontrol r egister 3 (liuccr3) h ex a ddress : 0 x 0f n 3 b it f unction t ype d efault d escription -o peration
xrt86vl34 153 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 119: liu c hannel c ontrol i nterrupt e nable r egister (liuccier) h ex a ddress : 0 x 0f n 4 b it f unction t ype d efault d escription -o peration 7 reserved ro 0 this bit is not used 6 dmoie_n r/w 0 change of transmit dmo (drive monitor output) condition inter - rupt enable: this bit permits the user to either enable or disable the ?change of transmit dmo condition? interrupt. if the user enables this interrupt, then the xrt86vl34 device will generate an interrupt any time when either one of the following events occur. 1. whenever the transmit section toggles the dmo status bit (bit 6 or register 0x0fn5) to ?1?. 2. whenever the transmit section toggles the dmo status bit (bit 6 or register 0x0fn5) to ?0?. 0 ? disables the ?change in the dmo condition? interrupt. 1 ? enables the ?change in the dmo condition? interrupt. 5 flsie_n r/w 0 fifo limit status interrupt enable: this bit permits the user to either enable or disable the ?fifo limit sta - tus? interrupt. if the user enables this interrupt, then the xrt86vl34 device will generate an interrupt when the jitter attenuator read/write fifo pointers are within +/- 3 bits. 0 = disables the ?fifo limit status? interrupt 1 = enables the ?fifo limit status? interrupt 4 reserved - - this bit is not used. 3 nlcdie_n r/w 0 change in network loop-code detection interrupt enable: this bit permits the user to either enable or disable the ?change in net - work loop-code detection? interrupt. if the user enables this interrupt, then the xrt86vl34 device will generate an interrupt any time when either one of the following events occur. 1. whenever the receive section (within xrt86vl34) detects the network loop-code (loop-up or loop-down depending on which loop-code the receive liu is configured to detect). 2. whenever the receive section (within xrt86vl34) no longer detects the network loop-code (loop-up or loop-down depending on which loop-code the receive liu is configured to detect). 0 ? disables the ?change in network loop-code detection? interrupt. 1 ? enables the ?change in network loop-code detection? interrupt. 2 reserved - - this bit is not used
xrt86vl34 154 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description n ote : register 0x0f n 4, 0x0f n 5 and 0x0f n 6 only work if the liu is placed in single rail mode. if done so, the framer block must also be placed in single rail mode in register 0xn101. 1 rlosie_n r/w 0 change of the receive los (loss of signal) defect condition inter - rupt enable: this bit permits the user to either enable or disable the ?change of the receive los defect condition? interrupt. if the user enables this inter - rupt, then the xrt86vl34 device will generate an interrupt any time when either one of the following events occur. 1. whenever the receive section (within xrt86vl34) declares the los defect condition. 2. whenever the receive section (within xrt86vl34) clears the los defect condition. 0 ? disables the ?change in the los defect condition? interrupt. 1 ? enables the ?change in the los defect condition? interrupt. 0 qrpdie_n r/w 0 change in qrss pattern detection interrupt enable: this bit permits the user to either enable or disable the ?change in qrss pattern detection? interrupt. if the user enables this interrupt, then the xrt86vl34 device will generate an interrupt any time when either one of the following events occur. 1. whenever the receive section (within xrt86vl34) detects the qrss pattern. 2. whenever the receive section (within xrt86vl34) no longer detects the qrss pattern. 0 ? disables the ?change in qrss pattern detection? interrupt. 1 ? enables the ?change in qrss pattern detection? interrupt. t able 119: liu c hannel c ontrol i nterrupt e nable r egister (liuccier) h ex a ddress : 0 x 0f n 4 b it f unction t ype d efault d escription -o peration
xrt86vl34 155 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 120: liu c hannel c ontrol s tatus r egister (liuccsr) h ex a ddress : 0 x 0f n 5 b it f unction t ype d efault d escription -o peration 7 reserved ro 0 6 dmo_n ro 0 driver monitor output (dmo) status: this read-only bit indicates whether or not the transmit section is currently declaring the dmo alarm condition. the transmit section will check the transmit output e1 line signal for bipolar pulses via the ttip and tring output signals. if the transmit section were to detect no bipolar signal for 128 consecu - tive bit-periods, then it will declare the transmit dmo alarm condi - tion. this particular alarm can be used to check for fault conditions on the transmit output line signal path. the transmit section will clear the transmit dmo alarm condition the instant that it detects some bipolar activity on the transmit out - put line signal. 0 = indicates that the transmit section of xrt86vl34 is not cur - rently declaring the transmit dmo alarm condition. 1 = indicates that the transmit section of xrt86vl34 is currently declaring the transmit dmo alarm condition. n ote : if the dmo interrupt is enabled (dmoie - bit d6 of register 0x0fn4), any transition on this bit will generate an interrupt. 5 fls_n ro 0 fifo limit status: this read-only bit indicates whether or not the xrt86vl34 is currently declaring the fifo limit status. this bit is set to a ?1? to indicate that the jitter attenuator read/write fifo pointers are within +/- 3 bits. 0 = indicates that the xrt86vl34 is not currently declaring the fifo limit status. 1 = indicates that the xrt86vl34 is currently declaring the fifo limit status. n ote : if the fifo limit status interrupt is enabled, (flsie bit - bit d5 of register 0x0fn4), any transition on this bit will generate an interrupt. 4 reserved - 0 this bit is not used
xrt86vl34 156 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 3 nlcd_n ro 0 network loop-code detection status bit: this bit operates differently in the manual or the automatic network loop-code detection modes. manual loop-up code detection mode (.i.e if nlcde1 = ?0? and nlcde0 = ?1?), this bit gets set to ?1? as soon as the loop-up code (?00001?) is detected in the receive data for longer than 5 seconds. this bit stays high as long as the receive e1 liu block detects the presence of the loop-up code in the receive data and it is reset to ?0? as soon as it stops receiving the loop-up code. if the nlcd interrupt is enabled, the xrt86vl34 will initiate an interrupt on every transition of the nlcd status bit. manual loop-down code detection mode (i.e., if nlcde1 = ?1? and nlcde0 = ?0?), this bit gets set to ?1? as soon as the loop-down code (?001?) is detected in the receive data for longer than 5 seconds. this bit stays high as long as the receive e1 liu block detects the presence of the loop-down code in the receive data and it is reset to ?0? as soon as it stops receiving the loop-down code. if the nlcd interrupt is enabled, the xrt86vl34 will initiate an interrupt on every transition of the nlcd status bit. automatic loop-code detection mode (i.e., if nlcde1 = ?1? and nlcde0 =?1?), the state of the nlcd sta - tus bit is reset to ?0? and the xrt86vl34 is programmed to monitor the receive input data for the loop-up code. this bit is set to a ?1? to indicate that the network loop code is detected for more than 5 seconds. simultaneously the remote loop-back condition is automatically activated and the xrt86vl34 is programmed to monitor the receive data for the network loop down code. the nlcd bit stays ?high? as long as the remote loop- back condition is in effect even if the chip stops receiving the loop- up code. remote loop-back is removed only if the xrt86vl34 detects the loop-down code ?001? pattern for longer than 5 sec - onds in the receive data. upon detecting the loop-down code ?001? pattern, the xrt86vl34 will reset the nlcd status bit and an inter - rupt will be generated if the nlcd interrupt enable bit is enabled. users can monitor the state of this bit to determine if the remote loop-back is activated. 2 reserved - 0 this bit is not used t able 120: liu c hannel c ontrol s tatus r egister (liuccsr) h ex a ddress : 0 x 0f n 5 b it f unction t ype d efault d escription -o peration
xrt86vl34 157 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 n ote : register 0x0f n 4, 0x0f n 5 and 0x0f n 6 only work if the liu is placed in single rail mode. if done so, the framer block must also be placed in single rail mode in register 0xn101. 1 rlos_n ro 0 receive loss of signal defect condition status: this read-only bit indicates whether or not the receive liu block is currently declaring the los defect condition. 0 = indicates that the receive section is not currently declaring the los defect condition. 1 = indicates that the receive section is currently declaring the los defect condition. n ote : if the rlosie bit (bit d1 of register 0x0fn4) is enabled, any transition on this bit will generate an interrupt. 0 qrpd_n ro 0 quasi-random pattern detection status: this read-only bit indicates whether or not the receive liu block is currently declaring the qrss pattern lock status. 0 = indicates that the xrt86vl34 is not currently declaring the qrss pattern lock. 1 = indicates that the xrt86vl34 is currently declaring the qrss pattern lock. n ote : if the qrpdie bit (bit d0 of register 0x0fn4) is enabled, any transition on this bit will generate an interrupt. t able 120: liu c hannel c ontrol s tatus r egister (liuccsr) h ex a ddress : 0 x 0f n 5 b it f unction t ype d efault d escription -o peration
xrt86vl34 158 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 121: liu c hannel c ontrol i nterrupt s tatus r egister (liuccisr) h ex a ddress : 0 x 0f n 6 b it f unction t ype d efault d escription -o peration 7 reserved ro 0 6 dmois_n rur/ wc 0 change of transmit dmo (drive monitor output) condition interrupt status: this reset-upon-read bit indicates whether or not the ?change of the transmit dmo condition? interrupt has occurred since the last read of this register. 0 = indicates that the ?change of the transmit dmo condition? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change of the transmit dmo condition? interrupt has occurred since the last read of this register. this bit is set to a ?1? every time when dmo_n status bit (bit 6 of register 0x0fn5) has changed since the last read of this register. n ote : users can determine the current state of the ?transmit dmo condition? by reading out the content of bit 6 within register 0x0fn5 5 flsis_n rur/ wc 0 fifo limit interrupt status: this reset-upon-read bit indicates whether or not the ?fifo limit? interrupt has occurred since the last read of this register. 0 = indicates that the ?fifo limit status? interrupt has not occurred since the last read of this register. 1 = indicates that the ?fifo limit status? interrupt has occurred since the last read of this register. this bit is set to a ?1? every time when fifo limit status bit (bit 5 of register 0x0fn5) has changed since the last read of this register. n ote : users can determine the current state of the ?fifo limit? by reading out the content of bit 5 within register 0x0fn5 4 reserved - - this bit is not used 3 nlcdis_n rur/ wc 0 change in network loop-code detection interrupt status: this reset-upon-read bit indicates whether or not the ?change in network loop-code detection? interrupt has occurred since the last read of this register. 0 = indicates that the ?change in network loop-code detection? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in network loop-code detection? interrupt has occurred since the last read of this register. this bit is set to a ?1? every time when nlcd status bit (bit 3 of reg - ister 0x0fn5) has changed since the last read of this register. n ote : users can determine the current state of the ?network loop- code detection? by reading out the content of bit 3 within register 0x0fn5 2 reserved - - this bit is not used
xrt86vl34 159 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 n ote : register 0x0f n 4, 0x0f n 5 and 0x0f n 6 only work if the liu is placed in single rail mode. if done so, the framer block must also be placed in single rail mode in register 0xn101. 1 rlosis_n rur/ wc 0 change of receive los (loss of signal) defect condition inter - rupt status: this reset-upon-read bit indicates whether or not the ?change of the receive los defect condition? interrupt has occurred since the last read of this register. 0 = indicates that the ?change of the receive los defect condi - tion? interrupt has not occurred since the last read of this register. 1 - indicates that the ?change of the receive los defect condition? interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the ?receive los defect condition? by reading out the contents of bit 1 (receive los defect condition status) within register 0xnfn5. 0 qrpdis_n rur/ wc 0 change in quasi-random pattern detection interrupt status: this reset-upon-read bit indicates whether or not the ?change in qrss pattern detection? interrupt has occurred since the last read of this register. 0 = indicates that the ?change in qrss pattern detection? interrupt has not occurred since the last read of this register. 1 = indicates that the ?change in qrss pattern detection? interrupt has occurred since the last read of this register. this bit is set to a ?1? every time when qrpd status bit (bit 0 of reg - ister 0x0fn5) has changed since the last read of this register. n ote : users can determine the current state of the ?qrss pattern detection? by reading out the content of bit 0 within register 0x0fn5 t able 121: liu c hannel c ontrol i nterrupt s tatus r egister (liuccisr) h ex a ddress : 0 x 0f n 6 b it f unction t ype d efault d escription -o peration
xrt86vl34 160 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 122: liu c hannel c ontrol c able l oss r egister (liuccccr) h ex a ddress : 0 x 0f n 7 b it f unction t ype d efault d escription -o peration 7 reserved ro 0 6 reserved ro 0 5-0 clos[5:0] ro 0 cable loss [5:0]: these bits represent the six bit receive selective equalizer setting which is also a binary word that represents the cable attenuation indication within 1db. clos5_n is the most significant bit (msb) and clos0_n is the least significant bit (lsb). t able 123: liu c hannel c ontrol a rbitrary r egister 1 (liuccar1) h ex a ddress : 0 x 0f n 8 b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6-0 arb_seg1 r/w 0 arbitrary transmit pulse shape, segment 1: these seven bits form the first of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbitrary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). n ote : arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0. t able 124: liu c hannel c ontrol a rbitrary r egister 2 (liuccar2) h ex a ddress : 0 x 0f n 9 b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6-0 arb_seg2 r/w 0 arbitrary transmit pulse shape, segment 2 these seven bits form the second of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbi - trary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). n ote : arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0.
xrt86vl34 161 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 125: liu c hannel c ontrol a rbitrary r egister 3 (liuccar3) h ex a ddress : 0 x 0f n a b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6-0 arb_seg3 r/w 0 arbitrary transmit pulse shape, segment 3 these seven bits form the third of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbitrary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). n ote : arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0. t able 126: liu c hannel c ontrol a rbitrary r egister 4 (liuccar4) h ex a ddress : 0 x 0f n b b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6-0 arb_seg4 r/w 0 arbitrary transmit pulse shape, segment 4 these seven bits form the forth of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbitrary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0. t able 127: liu c hannel c ontrol a rbitrary r egister 5 (liuccar5) h ex a ddress : 0 x 0f n c b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6-0 arb_seg5 r/w 0 arbitrary transmit pulse shape, segment 5 these seven bits form the fifth of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbitrary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0.
xrt86vl34 162 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 128: liu c hannel c ontrol a rbitrary r egister 6 (liuccar6) h ex a ddress : 0 x 0f n d b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6-0 arb_seg6 r/w 0 arbitrary transmit pulse shape, segment 6 these seven bits form the sixth of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbitrary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0. t able 129: liu c hannel c ontrol a rbitrary r egister 7 (liuccar7) h ex a ddress : 0 x 0f n e b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6 arb_seg7 r/w 0 arbitrary transmit pulse shape, segment 7 these seven bits form the seventh of the eight segments of the transmit shape pulse when the xrt86vl34 is configured in ?arbi - trary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0. t able 130: liu c hannel c ontrol a rbitrary r egister 8 (liuccar8) h ex a ddress : 0 x 0f n f b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6 arb_seg8 r/w 0 arbitrary transmit pulse shape, segment 8 these seven bits form the eight of the eight segments of the trans - mit shape pulse when the xrt86vl34 is configured in ?arbitrary mode?. these seven bits represent the amplitude of the nth channel's arbi - trary pulse in signed magnitude format with bit 6 as the sign bit and bit 0 as the least significant bit (lsb). arbitrary mode is enabled by writing to the eqc[4:0] bits in register 0x0fn0.
xrt86vl34 163 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 131: liu g lobal c ontrol r egister 0 (liugcr0) h ex a ddress : 0 x 0fe0 b it f unction t ype d efault d escription -o peration 7 sr r/w 0 single rail mode this bit must set to "1" for single rail mode to use liu diagnotic fea - tures. the framer section must be programmed as well in register 0xn101. 0 - dual rail 1 - single rail 6 ataos r/w 0 automatic transmit all ones upon rlos: this bit enables automatic transmission of all ones pattern upon detecting the receive loss of signal (rlos) condition. once this bit is enabled, the transmit e1 framer block will automat - ically transmit an all ?ones? data to the line for the channel that detects an rlos condition. 0 = disables the ?automatic transmit all ones? feature upon detect - ing rlos 1 = enables the ?automatic transmit all ones? feature upon detect - ing rlos 5 rclke r/w 0 receive clock data (framer bypass mode) 0 = rpos/rneg data is updated on the rising edge of rclk 1 = rpos/rneg data is updated on the falling edge of rclk 4 tclke r/w 0 transmit clock data (framer bypass mode) 0 = tpos/tneg data is sampled on the falling edge of tclk 1 = tpos/tneg data is sampled on the rising edge of tclk 3 datap r/w 0 data polarity 0 = transmit input and receive output data is active ?high? 1 = transmit input and receive output data is active ?low? 2 reserved this bit is not used
xrt86vl34 164 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description 1 gie r/w 0 global interrupt enable: this bit allows users to enable or disable the global interrupt gener - ation for all channels within the e1 liu block. once this global inter - rupt is disabled, no interrupt will be generated to the microprocessor interrupt pin even when the individual ?source? interrupt status bit pulses ?high?. if this global interrupt is enabled, users still need to enable the indi - vidual ?source? interrupt in order for the e1 liu block to generate an interrupt to the microprocessor pin. 0 - disables the global interrupt generation for all channels within the e1 liu block. 1 - enables the global interrupt generation for all channels within the e1 liu block. 0 sreset r/w 0 software reset p registers: this bit allows users to reset the xrt86vl34 device. writing a ?1? to this bit and keeping it at ?1? for longer than 10s initiates a device reset through the microprocessor interface. once the xrt86vl34 is reset, all internal circuits are placed in the reset state except the microprocessor register bits. 0 = disables software reset to the xrt86vl34 device. 1 = enables software reset to the xrt86vl34 device. t able 132: liu g lobal c ontrol r egister 1 (liugcr1) h ex a ddress : 0 x 0fe1 b it f unction t ype d efault d escription -o peration 7 reserved r/w 0 6 reserved r/w 0 5-4 gauge [1:0] r/w 00 wire gauge selector [1:0]: this bit together with guage0 bit (bit 4 within this register) are used to select the wire gauge size as shown in the table below. t able 131: liu g lobal c ontrol r egister 0 (liugcr0) h ex a ddress : 0 x 0fe0 b it f unction t ype d efault d escription -o peration gauge1 0 1 1 0 gauge0 0 1 0 1 wire size 22 and 24 gauge 26 gauge 24 gauge 22 gauge
xrt86vl34 165 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 3 e1 arbitrary enable e1 arbitrary mode enable this bit is used to enable the arbitrary pulse generators for shaping the transmit pulse shape for e1 mode. if this bit is set to ?1?, all 4 channels will be configured for the arbitrary mode. however, each channel?s pulse shape is individually controlled by programming the 8 transmit pulse shape segments (channel registers 0x0fn8 through 0x0fnf) ?0? = disabled (normal e1 pulse shape itu g.703) ?1? = arbitrary pulse enabled 2 rxmute r/w 0 receive output mute: this bit permits the user to configure the receive e1 block to auto - matically pull its recovered data output pins to gnd anytime (and for the duration that) the receive e1 liu block declares the los defect condition. in other words, if this feature is enabled, the receive e1 liu block will automatically ?mute? the recovered data that is being routed to the receive e1 framer block anytime (and for the duration that) the receive e1 liu block declares the los defect condition. 0 ? disables the ?muting upon los? feature. 1 ? enables the ?muting upon los? feature. n ote : the receive clock is not muted when this feature is enabled. 1 exlos extended los enable: this bit allows users to extend the number of zeros at the receive input of each channel before rlos is declared. when extended los is enabled, the receive e1 liu block will declare rlos condition when it receives 4096 number of consecu - tive zeros at the receive input. when extended los is disabled, the receive e1 liu block will declare rlos condition when it receives 175 number of consecu - tive zeros at the receive input. 0 = disables the extended los feature. 1 = enables the extended los feature. 0 ict r/w 0 in-circuit-testing enable: this bit allows users to tristate the output pins of all channels for in- circuit testing purposes. when in-circuit-testing is enabled, all output pins of the xrt86vl34 are ?tri-stated?. when in-circuit-testing is disabled, all output pins will resume to normal condition. 0 = disables the in-circuit-testing feature. 1 = enables the in-circuit-testing feature. t able 132: liu g lobal c ontrol r egister 1 (liugcr1) h ex a ddress : 0 x 0fe1 b it f unction t ype d efault d escription -o peration
xrt86vl34 166 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 133: liu g lobal c ontrol r egister 2 (liugcr2) h ex a ddress : 0 x 0fe2 b it f unction t ype d efault d escription -o peration 7 force to "0" r/w 0 set to "0" 6 rxtcntl r/w 0 receive termination select control this bit sets the liu to control the rxtsel function with either the individual channel register bit or the global hardware pin. 0 = control of the receive termination is set to the register bits 1 = control of the receive termination is set to the hardware pin 5-0 reserved r/w 0 this bit is not used t able 134: liu g lobal c ontrol r egister 3 (liugcr3) h ex a ddress : 0 x 0fe4 b it f unction t ype d efault d escription -o peration 7-6 mclknt1[1:0] r/w 00 master t1 output clock reference [1:0] these two bits allow users to select the programmable output clock rates for the t1mclknout pin, according to the table below. 5-4 mclkne1[1:0] r/w 00 master e1 output clock reference [1:0]: these two bits allow users to select the programmable output clock rates for the e1mclknout pin, according to the table below: 3-0 reserved r/w 0 this bit is not used. mclk n t1[1:0] c lock r ate of t he t1mclk n out o utput p in 00 1.544mhz 01 3.088mhz 10 6.176mhz 11 12.352mhz mclk n e1[1:0] c lock r ate of t he e1mclk n out o utput p in 00 2.048mhz 01 4.096mhz 10 8.192mhz 11 16.384mhz
xrt86vl34 167 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 t able 135: liu g lobal c ontrol r egister 4 (liugcr4) h ex a ddress : 0 x 0fe9 b it f unction t ype d efault d escription -o peration 7-4 reserved r/w 0 3-0 clksel[3:0] r/w 1100 clock select input [3:0] these four bits allow users to select the programmable input clock rates for the mclkin input pin, according to the table below. n ote : user must provide any one of the above clock frequencies to the mclkin input pin for the device to be functional. clksel[3:0] c lock r ate of t he mclkin i nput p in 0000 2.048mhz 0001 1.544mhz 0010 8khz 0011 16khz 0100 56khz 0101 64khz 0110 128khz 0111 256khz 1000 4.096mhz 1001 3.088mhz 1010 8.192mhz 1011 6.176mhz 1100 16.384mhz 1101 12.352mh 1110 2.048mhz 1111 1.544mhz
xrt86vl34 168 rev. v1.2.0 quad t1/e1/j1 framer/liu combo - e1 register description t able 136: liu g lobal c ontrol r egister 5 (liugcr5) h ex a ddress : 0 x 0fea b it f unction t ype d efault d escription -o peration 4-7 reserved - 0 these bits are reserved 3 gchis3 rur/ wc 0 global channel 3 interrupt status indicator this reset-upon-read bit field indicates whether or not an interrupt has occurred on channel 3 within the xrt86vl34 device since the last read of this register. 0 = indicates that no interrupt has occurred on channel 3 within the xrt86vl34 device since the last read of this register. 1 = indicates that an interrupt has occurred on channel 3 within the xrt86vl34 device since the last read of this register. 2 gchis2 rur/ wc 0 global channel 2 interrupt status indicator this reset-upon-read bit field indicates whether or not an interrupt has occurred on channel 2 within the xrt86vl34 device since the last read of this register. 0 = indicates that no interrupt has occurred on channel 2 within the xrt86vl34 device since the last read of this register. 1 = indicates that an interrupt has occurred on channel 2 within the xrt86vl34 device since the last read of this register. 1 gchis1 rur/ wc 0 global channel 1 interrupt status indicator this reset-upon-read bit field indicates whether or not an interrupt has occurred on channel 1 within the xrt86vl34 device since the last read of this register. 0 = indicates that no interrupt has occurred on channel 1 within the xrt86vl34 device since the last read of this register. 1 = indicates that an interrupt has occurred on channel 1 within the xrt86vl34 device since the last read of this register. 0 gchis0 rur/ wc 0 global channel 0 interrupt status indicator this reset-upon-read bit field indicates whether or not an interrupt has occurred on channel 0 within the xrt86vl34 device since the last read of this register. 0 = indicates that no interrupt has occurred on channel 0 within the xrt86vl34 device since the last read of this register. 1 = indicates that an interrupt has occurred on channel 0 within the xrt86vl34 device since the last read of this register.
xrt86vl34 169 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 ordering information package dimensions p roduct n umber p ackage o perating t emperature r ange xrt86vl34ib 225 lead pbga -40 0 c to +85 0 c e 225 ball plastic ball grid array (19.0 mm x 19.0 mm, 1.0mm pitch pbga) rev. 1.00 symbol min max min max a 0.049 0.096 1.24 2.45 a1 0.016 0.024 0.40 0.60 a2 0.013 0.024 0.32 0.60 a3 0.020 0.048 0.52 1.22 d 0.740 0.756 18.80 19.20 d1 0.669 bsc 17.00 bsc d2 0.665 0.669 16.90 17.00 b 0.020 0.028 0.50 0.70 e 0.039 bsc 1.00 bsc inches millimeters note: the control dimension is in millimeter. 1 2 4 3 7 86 5 1 7 1 6 1 4 1 5 1 2 1 3 1 1 1 0 9 1 8 a b c d e f g h j k l m n p r t u v d d1 d d1 a1 feature / mark d2 a a 1 a 2 a 3 e b (a1 corner feature is mfger option) seating plane
170 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the li fe support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet january 2007. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. xrt86vl34 quad t1/e1/j1 framer/liu combo - e1 register description rev. v1.2.0 revision history r evision # d ate d escription v1.2.0 january 25, 2007 release to production.

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